1
Jama I Barreh, Robert T Golla: Fetch speculation in a multithreaded processor. Sun Microsystems, Lawrence J Merkel, Meyertons Hood Kivlin Kowert & Goetzel P c, February 27, 2007: US07185178 (55 worldwide citation)

In one embodiment, a processor comprises an instruction cache and a fetch generator circuit coupled thereto. The fetch generator circuit is configured to generate at least one fetch request to the instruction cache for at least one of the plurality of threads. The fetch generator circuit is also con ...


2
Jeffrey S Brooks, Christopher H Olson, Robert T Golla: Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processor. Sun Microsystems, Robert C Kowert, Anthony M Petro, Meyertons Hood Kivlin Kowert & Goetzel P C, January 13, 2009: US07478225 (43 worldwide citation)

An apparatus and method to support pipelining of variable-latency instructions in a multithreaded processor. In one embodiment, a processor may include instruction fetch logic configured to issue a first and a second instruction from different ones of a plurality of threads during successive cycles. ...


3
Carl D Dietz, Robert T Golla, Christopher H Olson: Method and system for minimizing branch misprediction penalties within a processor. International Business Machines Corporation, Michael A Davis Jr, Andrew J Dillon, May 27, 1997: US05634103 (40 worldwide citation)

A method and system within a processor are disclosed for executing selected instructions among a number of instructions stored within a memory, wherein the processor has a maximum of instructions that can dispatched for execution during each processor cycle. A subset of the instructions are fetched ...


4
Robert T Golla, Mark A Luttrell: Efficient utilization of a store buffer using counters. Sun Microsystems, Osha • Liang, April 14, 2009: US07519796 (25 worldwide citation)

An apparatus and method for efficiently managing store buffer operations is described in connection with a multithreaded multiprocessor chip. A CMT processor keeps track of stores by maintaining two store counters in the instruction fetch unit (IFU). A speculative store counter in the IFU tracks sto ...


5
Robert T Golla, Mark A Luttrell: Handling cache misses by selectively flushing the pipeline. Sun Microsystems, Osha • Liang, March 24, 2009: US07509484 (18 worldwide citation)

An apparatus and method for efficiently managing data cache load misses is described in connection with a multithreaded, pipelined multiprocessor chip. A CMT processor keeps track of load misses for each thread by issuing a load miss signal each time a load instruction to the data cache misses. A de ...


6
Ricky C Hetherington, Gregory F Grohoski, Robert T Golla: Apparatus and method for fine-grained multithreading in a multipipelined processor core. Sun Microsystems, Robert C Kowert, Anthony M Petro, Meyertons Hood Kivlin Kowert & Goetzel P C, July 15, 2008: US07401206 (16 worldwide citation)

An apparatus and method for fine-grained multithreading in a multipipelined processor core. According to one embodiment, a processor may include instruction fetch logic configured to assign a given one of a plurality of threads to a corresponding one of a plurality of thread groups, where each of th ...


7
Bryan Black, Marvin A Denman, Lee E Eisen, Robert T Golla, Albert J Loper Jr, Soummya Mallick, Russell A Reininger: Method and system for recoding noneffective instructions within a data processing system. International Business Machines Corporation, Michael A Davis Jr, Andrew J Dillon, April 8, 1997: US05619408 (14 worldwide citation)

A method and system are disclosed for processing instructions within a data processing system including a processor having a plurality of execution units. According to the method of the present invention, a number of instructions stored within a memory within the data processing system are retrieved ...


8
Gregory F Grohoski, Paul J Jordan, Mark A Luttrell, Zeid Hartuon Samoail, Robert T Golla: System and method to manage address translation requests. Oracle America, Robert C Kowert, Meyertons Hood Kivlin Kowert & Goetzel P C, October 30, 2012: US08301865 (14 worldwide citation)

A system and method for servicing translation lookaside buffer (TLB) misses may manage separate input and output pipelines within a memory management unit. A pending request queue (PRQ) in the input pipeline may include an instruction-related portion storing entries for instruction TLB (ITLB) misses ...


9
Robert T Golla, Ricky C Hetherington: Method and apparatus for power throttling in a multi-thread processor. Sun Microsystems, Meyertons Hood Kivlin Kowert & Goetzel P C, Robert C Kowert, Rory D Rankin, February 12, 2008: US07330988 (12 worldwide citation)

A method and apparatus for controlling power consumption in a processor. In one embodiment, a processor includes a pipeline. The pipeline includes logic for fetching instructions, issuing instructions, and executing instructions. The processor also includes a power management unit. The power managem ...


10
Robert T Golla, Gregory F Grohoski: Multithreaded processor including a functional unit shared between multiple requestors and arbitration therefor. Sun Microsystems, Robert C Kowert, Meyertons Hood Kivlin Kowert & Goetzel P C, May 12, 2009: US07533248 (10 worldwide citation)

A multithreaded processor including a shared functional unit. In one embodiment, the multithreaded processor includes a functional unit coupled to a multithreaded instruction source that may request access to use the functional unit. The multithreaded processor may also include a processing unit tha ...