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Robert P Fletcher, David M Stein, Irving Wladawsky Berger: Three level memory hierarchy using write and share flags. International Business Machines Corporation, Jack M Arnold, April 10, 1984: US04442487 (133 worldwide citation)

A multiprocessing three level memory hierarchy implementation is described which uses a "write" flag and a "share" flag per page of information stored in a level three main memory. These two flag bits are utilized to communicate from main memory at level three to private and shared caches at memory ...


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Robert P Fletcher: Multiprocessing system including a shared cache. International Business Machines Corporation, Jack M Arnold, April 24, 1984: US04445174 (126 worldwide citation)

A control system for interlocking processors in a multiprocessing organization. Each processor has its own high speed store in buffer (SIB) cache and each processor shares a common cache with the other processors. The control system insures that all processors access the most up-to-date copy of memo ...


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Robert P Fletcher: Second level cache replacement method and apparatus. International Business Machines Corporation, Bernard M Goldman, August 7, 1984: US04464712 (77 worldwide citation)

The disclosure controls the replacement selection of entries in a second level (L2) cache directory of a storage hierarchy using replaced and hit addresses of a dynamic look-aside translation buffer (DLAT) at the first level (L1) in the hierarchy which receives CPU storage requests along with the CP ...


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Robert P Fletcher: Cache sharing control in a multiprocessor. International Business Machines Corporation, Bernard M Goldman, November 20, 1984: US04484267 (47 worldwide citation)

The hybrid cache control provides a sharing (SH) flag with each line representation in each private CP cache directory in a multiprocessor (MP) to uniquely indicate for each line in the associated cache whether it is to be handled as a store-in-cache (SIC) line when its SH flag is in non-sharing sta ...


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Robert P Fletcher, Daniel B Martin: Page controlled cache directory addressing. International Business Machines Corporation, Bernard M Goldman, April 3, 1984: US04441155 (47 worldwide citation)

The described embodiment modifies cache addressing in order to decrease the cache miss rate based on a statistical observation that the lowest and highest locations in pages in main storage page frames are usually accessed at a higher frequency than intermediate locations in the pages. Cache class a ...


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Robert P Fletcher: Multiprocessor cache replacement under task control. International Business Machines Corporation, Bernard M Goldman, July 31, 1984: US04463420 (41 worldwide citation)

The disclosure describes a novel cache directory entry replacement method and means for central processors (CPs) in a multiprocessor (MP) based on task identifiers (TIDs) provided in each directory entry to identify the program task which inserted the respective entry. A remote TID register is provi ...


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