1
Robert P Colwell, John O Donnell, David B Papworth, Paul K Rodman: Hierarchical priority branch handling for parallel execution in a parallel processor. Multiflow Computer, Hale and Dorr, May 23, 1989: US04833599 (207 worldwide citation)

In a parallel data processing system having a plurality of separately operating arithmetic processing units, a method and apparatus allows a plurality of branch instructions to be operated upon in a single machine cycle. The branch instructions have associated therewith a hierarchical priority syste ...


2
Glenn J Hinton, David B Papworth, Andrew F Glew, Michael A Fetterman, Robert P Colwell: Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer. Intel Corporation, Blakely Sokoloff Taylor & Zafman, February 24, 1998: US05721855 (179 worldwide citation)

A pipelined method for executing instructions in a computer system. The present invention includes providing multiple instructions as a continuous stream of operations. This stream of operations is provided in program order. In one embodiment, the stream of operations is provided by performing an in ...


3
Robert P Colwell, John O Donnell, David B Papworth, Paul K Rodman: Instruction storage and cache miss recovery in a high speed multiprocessing parallel processing apparatus. Digital Equipment Corporation, Denis G Maloney, Barry Young, Ron Myrick, January 12, 1993: US05179680 (107 worldwide citation)

A method and apparatus for storing an instruction word in a compacted form on a storage media, the instruction word having a plurality of instruction fields, features associating with each instruction word, a mask word having a length in bits at least equal to the number of instruction fields in the ...


4
Robert P Colwell, John O Donnell, David B Papworth, Paul K Rodman: Instruction storage method with a compressed format using a mask word. Digital Equipment Corporation, Finnegan Henderson Farabow Garrett and Dunner, October 15, 1991: US05057837 (98 worldwide citation)

A method and apparatus for storing an instruction word in a compacted form on a storage media, the instruction word having a plurality of instruction fields, features associating with each instruction word, a mask word having a length in bits at least equal to the number of instruction fields in the ...


5
Robert P Colwell, John O Donnell, David B Papworth, Paul K Rodman: Virtual address table look aside buffer miss recovery method and apparatus. Multiflow Computer, Hale and Dorr, April 24, 1990: US04920477 (84 worldwide citation)

A data processor has a central processing unit and at least one pipelined memory controller circuitry. The central processing unit addresses data in the memory using a virtual address memory table lookaside buffer and features a data miss recovery circuitry wherein, after a memory access error condi ...


6
Shahrokh Shahidzadeh, Bryant E Bigbee, David B Papworth, Frank Binns, Robert P Colwell: Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessor. Intel Corporation, Seth Z Kalson, February 19, 2002: US06349380 (64 worldwide citation)

A microprocessor for providing an extended linear address of more than 32 bits. The extended linear address may be provided by concatenating a linear address with a segment selector extension, or by concatenating the values from two registers. Hierarchical translation of a linear address to a physic ...


7
David B Papworth, Andrew F Glew, Glenn J Hinton, Robert P Colwell, Michael A Fetterman, Shantanu R Gupta, James S Griffith: Method and apparatus for dynamic allocation of multiple buffers in a processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 7, 1998: US05778245 (60 worldwide citation)

A method and apparatus for dynamically allocating entries of microprocessor resources to particular instructions in an efficient manner to efficiently utilize buffer size and resources. The pipelined and superscalar microprocessor is capable of speculatively executing instructions and also out-of-or ...


8
David W Clift, James M Arnold, Robert P Colwell, Andrew F Glew: Floating point register alias table FXCH and retirement floating point register array. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 12, 1996: US05499352 (52 worldwide citation)

A Register Alias Table (RAT), including a retirement floating point RAT array, for floating point register renaming within a superscalar microprocessor capable of speculative execution. The RAT provides register renaming floating point registers to take advantage of a larger physical register set th ...


9
Robert P Colwell, Andrew F Glew, Atiq A Bajwa, Glenn J Hinton, Michael A Fetterman: Flag renaming and flag masks within register alias table. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 4, 2000: US06047369 (51 worldwide citation)

A mechanism and method for renaming flags within a register alias table ("RAT") to increase processor parallelism and also providing and using flag masks associated with individual instructions. In order to reduce the amount of data dependencies between instructions that are concurrently processed, ...


10
Robert P Colwell, Andrew F Glew: Partial width stalls within register alias table. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 29, 1995: US05446912 (50 worldwide citation)

A partial width stall mechanism within a register alias table unit (RAT) for handling partial width data dependencies of a given set of operations issued simultaneously within a superscalar microprocessor. Operations of the given set are presented to the RAT in program order and partial width data d ...