1
Martin Langhammer, Kwan Yee Martin Lee, Orang Azgomi, Keone Streicher, Robert L Pelt: Specialized processing block for programmable logic device. Altera Corporation, Ropes & Gray, Jeffrey H Ingerman, October 18, 2011: US08041759 (20 worldwide citation)

A specialized processing block for a programmable logic device incorporates a fundamental processing unit that performs a sum of two multiplications, adding the partial products of both multiplications without computing the individual multiplications. Such fundamental processing units consume less a ...


2
Benjamin Esposito, Robert L Pelt: Hybrid multipliers implemented using DSP circuitry and programmable logic circuitry. Altera Corporation, Ropes & Gray, Alexander Shvarts, Robert R Jackson, September 11, 2007: US07269617 (5 worldwide citation)

A user logic design to hardware application is provided that efficiently implements in a PLD a user logic design multiplier using both programmable logic circuitry and one or more multipliers embedded in DSP circuitry integrated in the PLD. A smaller DSP multiplier may be used by implementing the us ...


3
Ting Lu, Robert L Pelt, Bradley L Taylor: Integrated debugging within an integrated circuit having an embedded processor. Xilinx, Kevin T Cuenot, November 26, 2013: US08595561 (3 worldwide citation)

A method of debugging within an integrated circuit (IC) that includes an embedded processor can include detecting an event within a circuit of the IC that is external to the processor and, responsive to detecting the event, initiating a debug function within the processor. Similarly, responsive to d ...


4
Robert L Pelt, Sam Hedinger: Bridge circuitry for communications with dynamically reconfigurable circuits. Altera Corporation, Treyz Law Group, Vineet Dixit, October 11, 2016: US09465763

A bridge circuit may be used to interface between dynamically reconfigurable circuitry and dedicated circuitry or other circuitry having static configurations during normal operation of the device. The bridge circuit may include interface circuitry coupled between first and second interfaces that co ...


5
Sam Hedinger, Robert L Pelt: Methods and systems for AXI ID compression. Altera Corporation, Fletcher Yoder P C, June 28, 2016: US09379980

Methods and systems for AXI ID compression are disclosed. Bus transaction data and an M-bit ID associated with the bus transaction data are transmitted by a master device via a bus to an ID mapper. The ID mapper is used to select, based on the M-bit ID, an N-bit ID from a plurality of N-bit IDs, whe ...