1
Peter D MacWilliams, Robert L Farrell, Adalberto Golbert, Itzik Silas: Second level cache controller unit and system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, October 11, 1994: US05355467 (136 worldwide citation)

A second level cache memory controller, implemented as an integrated circuit unit, operates in conjunction with a secondary random access cache memory and a main memory (system) bus controller to form a second level cache memory subsystem. The subsystem is interfaced to the local processor (CPU) bus ...


2
Raymond S Tetrick, John Beaston, Robert L Farrell, Alireza Sarabi, Sudarshan Balachandran, Edwin L Jacks Jr, Steven D Kassel: High speed parallel bus and data transfer method. Intel Corporation, Blakely Sokoloff Taylor & Zafman, February 11, 1986: US04570220 (124 worldwide citation)

A multiple bus system architecture and improved data transfer methods are disclosed for transferring data between a plurality of data processing resources. The bus structure of the present invention includes both a parallel and serial bus which interconnects data processing units and peripheral devi ...


3
Peter D MacWilliams, Clair C Webb, Robert L Farrell: Cache memory integrated circuit for use with a synchronous central processor bus and an asynchronous memory bus. Intel Corporation, July 13, 1993: US05228134 (84 worldwide citation)

An integrated circuit implements a cache static random access memory (SRAM) storage element which includes a central processor unit (CPU) bus interface incorporating multiplexers and buffers circuits for optimizing burst read and write operations across the CPU bus. Theses circuits allow a full cach ...


4
Peter D MacWilliams, Clair C Webb, Robert L Farrell: Cache subsystem for microprocessor based computer system with synchronous and asynchronous data path. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 8, 1994: US05293603 (65 worldwide citation)

An integrated circuit, for use as a cache subsystem, implements a cache static random access memory (SRAM) storage array, a central processor unit (CPU) bus interface and a main memory bus interface. The CPU bus and main memory bus interfaces include multiplexers, buffers, and local control for opti ...


5
Robert L Farrell, Alireza Sarabi, Raymond S Tetrick: High speed synchronous/asynchronous local bus and data transfer method. Intel Corporation, Blakely Sokoloff Taylor & Zafman, February 21, 1989: US04807109 (50 worldwide citation)

A high speed local synchronous bus is disclosed for coupling processors within a multi-processor system such that local memory and secondary processing resources may be accessed without impacting data traffic along the bus. The local bus employs a message control method and apparatus which includes ...


6
Varghese George, Robert L Farrell: Multiple operating frequencies in a processor. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 31, 2004: US06785829 (35 worldwide citation)

A power control circuit an corresponding technique for adjusting operating frequency and/or supply voltage in sections of a single electronic device while maintaining substantially constant operating frequency and/or supply voltage in the other sections in the electronic device. Such control is base ...


7
Leslie E Cline, Xia Dai, Varghese George, Robert L Farrell: System and method for selecting a frequency and voltage combination from a table using a selection field and a read-only limit field. Intel Corporation, John F Travis, January 17, 2006: US06988211 (24 worldwide citation)

A selectable control over multiple clock frequency/voltage level combinations that can be activated in a processor. A table can be placed in hardware that defines multiple combinations of CPU clock frequency and CPU operating voltage. By placing the table in hardware, it can be assured that all the ...


8
Jerrold V Hauck, Randy R Dunton, Robert L Farrell: Integrating data scaling and buffering functions to minimize memory requirement. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 18, 2000: US06091426 (11 worldwide citation)

A scaling circuit residing on a single silicon substrate includes a buffer for storing a plurality of partially scaled data. A multiplier is provided for multiplying a weight signal with each of a plurality of input data to produce a plurality of weighted data. An adder is coupled to (1) the multipl ...


9
Peter D MacWilliams, Dror Avni, Avi Liebermensch, Anan Baransy, Robert L Farrell: Parallel multistage synchronization method and apparatus. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 30, 1996: US05488639 (8 worldwide citation)

A method and apparatus for synchronizing an asynchronous signal to a clock signal. The apparatus includes an enable generator, first, second and third sampling circuits, a selecting circuit, and can include a latching circuit. The enable generator is coupled to the first sampling circuit by a first ...


10
Robert L Farrell: Method and apparatus for maintaining audio sample correlation. Intel Corporation, Kenyon & Kenyon, September 14, 1999: US05953411 (3 worldwide citation)

Input/output sample correlation is achieved through the use of first and second correlation tags appended to input and output buffers, respectively. As an output buffer of output samples is prepared, the first correlation tag identifies one of tie output samples in that buffer. As input samples are ...