1
Gregory M Papadopoulos, Rishiyur S Nikhil, Robert J Greiner, Arvind: Data processing system with synchronization coprocessor for multiple threads. Massachusetts Institute of Technology, Hamilton Brook Smith & Reynolds, July 4, 1995: US05430850 (118 worldwide citation)

A multiprocessor system comprises a plurality of processing nodes, each node processing multiple threads of computation. Each node includes a data processor which sequentially processes blocks of code, each block defining a thread of computation. The code includes instructions to send start messages ...


2
Gregory M Papadopoulos, Rishiyur S Nikhil, Robert J Greiner, Arvind: Data processing system with synchronization coprocessor for multiple threads. Massachusetts Institute of Technology, Hamilton Brook Smith & Reynolds P C, September 24, 1996: US05560029 (86 worldwide citation)

A multiprocessor system comprises a plurality of processing nodes, each node processing multiple threads of computation. Each node includes a data processor which sequentially processes blocks of code, each block defining a thread of computation. The code includes instructions to send start messages ...


3
Gurbir Singh, Robert J Greiner, Stephen S Pawlowski, David L Hill, Donald D Parker: Quad pumped bus architecture and protocol. Intel Corporation, Antonelli Terry Stout & Kraus, July 29, 2003: US06601121 (63 worldwide citation)

A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of th ...


4
David L Hill, Paul D Breuder, Robert J Greiner, Derek T Bachand: External bus transaction scheduling system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, May 4, 2004: US06732242 (40 worldwide citation)

A transaction management system is described for scheduling requests on an external bus. The system includes a number of queue registers to store requests and a controller coupled to queue registers to schedule external bus transactions for an agent that processes read requests, prefetch requests an ...


5
Keshavan K Tiruvallur, Douglas M Carmean, Robert J Greiner, Muntaquim Chowdhury, Madhavan Parthasarathy: Method and apparatus for multi-mode fencing in a microprocessor system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 16, 2004: US06708269 (28 worldwide citation)

In a multi-threaded system, such as in a multi-processor system, different types of fences are provided to force completion of programmatically earlier instructions in a program. The types of fences can be thread-specific, and different types of fences are used based on different kinds of conditions ...


6
Gurbir Singh, Robert J Greiner, Stephen S Pawlowski, David L Hill, Donald D Parker: Quad pumped bus architecture and protocol. Intel Corporation, Antonelli Terry Stout & Kraus, August 19, 2003: US06609171 (16 worldwide citation)

A bidirectional multidrop processor bus is connected to a plurality of bus agents. Bus throughput can be increased by operating the bus in a multi pumped signaling mode in which multiple information elements are driven onto a bus by a driving agent at a rate that is a multiple of the frequency of th ...


7
Edward Allyn Burton, Robert J Greiner, Anant S Deval, Douglas Robert Huard: Multi-phase voltage regulator with phases ordered by lowest phase current. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 19, 2008: US07414383 (15 worldwide citation)

While firing a number of phases of a multi-phase switching voltage regulator in a sequence, a determination is made as to which one of the phases has the lowest phase current. Then, the next phase, to be fired in the sequence, is selected as the one that has been determined to have the lowest phase ...


8
Gurbir Singh, Robert J Greiner, Stephen S Pawlowski, David L Hill, Donald D Parker: Enhanced highly pipelined bus architecture. Intel Corporation, Jeffery S Draeger, June 14, 2005: US06907487 (11 worldwide citation)

A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a control interface to drive a control signal at a clock frequency, an address bus interface to drive address elements at twice the clock frequency, and a data bus interface to dr ...


9
Edward A Burton, Robert J Greiner, Anant S Deval, Douglas R Huard, Jeremy J Shrall, Arun R Ramadorai, Benson D Inkley, Martin M Chang: Power control unit with digitally supplied system parameters. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 23, 2010: US07685441 (10 worldwide citation)

Methods and apparatuses provide voltage regulation for a processor. Control or configuration parameters for a voltage regulator (VR) are provided digitally over a configuration bus to a VR controller. The parameters may be provided directly from a storage element, or via a processing element or proc ...


10
Gurbir Singh, Robert J Greiner, Stephen S Pawlowski, David L Hill, Donald D Parker: Response and data phases in a highly pipelined bus architecture. Intel Corporation, Jeffrey S Draeger, October 12, 2004: US06804735 (10 worldwide citation)

A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a target ready interface, a set of response interfaces for a set of response signals, and a data bus busy interface, and a bus clock interface for a bus clock signal. The bus agen ...