1
Robert J Bosnyak, Robert J Drost, David M Murata: Fully complementary differential output driver for high speed digital communications. Sun Microsystems, Forrest E Gunnison, Skjerven Morrill MacPherson Franklin & Friel, June 16, 1998: US05767699 (124 worldwide citation)

A terminating element is connected between the terminating ends of a transmission line pair. A switching mechanism coupled to the originating ends of the transmission line pair steers a constant current through the transmission line pair. In response to input control signals, the switching mechanism ...


2
John E Cunningham, Ashok V Krishnamoorthy, Ronald Ho, Robert J Drost: Transparent switch using optical and electrical proximity communication. Sun Microsystems, Park Vaughan & Fleming, April 8, 2008: US07356213 (89 worldwide citation)

Embodiments of a switch are described. This switch includes input ports configured to receive signals (which include data) and output ports configured to output the signals. In addition, the switch includes switching elements and a flow-control mechanism, which is configured to provide flow-control ...


3
Robert J Drost, Jose M Cruz, Robert J Bosnyak: Clock duty cycle control technique. Sun Microsystems, William W Holloway, Skjerven Morrill MacPherson Franklin & Friel L, July 4, 2000: US06084452 (50 worldwide citation)

An apparatus adjusts the duty cycle of a single-ended clock signal. The single-ended clock signal oscillates between first and second voltages. The apparatus includes an error indication circuit, a duty cycle error measurement circuit and a duty cycle adjuster. The error indication circuit includes ...


4
Ramin Farjad Rad, Robert J Drost: Phase detector for clock synchronization and recovery. Sun Microsystems, Forrest E Gunnison, Skjerven Morrill MacPherson Franklin & Friel, August 25, 1998: US05799048 (50 worldwide citation)

A clock recovery circuit employing a phase-locked loop design includes an N-to-1 multiplexer (MUX) coupled to a series of N latches which allows data to sampled at a frequency N times that of the clock. Incoming data is latched by each of the N latches, where each latch is clocked at a different pha ...


5
Robert J Drost, Robert J Bosnyak: Controlled phase noise generation method for enhanced testability of clock and data generator and recovery circuits. Sun Microsystems, Finnegan Henderson Farabow Garrett & Dunner L, June 13, 2000: US06076175 (34 worldwide citation)

A transmitter/receiver chip includes circuitry for testing the bit error rate of the chip. A controlled amount of noise is introduced to the chip to vary a timing parameter of a transmit clock, resulting in an increase in a bit error rate of the chip. Artificially increasing the bit error rate of th ...


6
Robert J Drost, Robert J Bosnyak, Jose M Cruz: On-chip differential resistance technique with noise immunity and symmetric resistance. Sun Microsystems, Michael P Noonan, Skjerven Morrill MacPherson Franklin & Friel L, September 21, 1999: US05955911 (34 worldwide citation)

An on-chip resistance to an input current of an input signal includes a parallel transistor resistor and a control circuit for biasing the transistors of the parallel transistor resistor. The parallel transistor resistor includes first and second transistors of first and second types. Each transisto ...


7
David M Murata, Robert J Bosnyak, Robert J Drost: System and method for serial to parallel data conversion using delay line. Sun Microsystems, Robert Scott Hauser, July 7, 1998: US05777567 (30 worldwide citation)

A serial data to parallel data converter is disclosed which has the advantage of accurately converting high frequency serial data to parallel data while using clock signals operating at a relatively low frequency. A low bit error rate is achieved by avoiding the use of multiple high speed clock line ...


8
Robert J Drost, Robert Bosnyak, Jose M Cruz: Adaptive equalization technique using twice sampled non-return to zero data. Sun Microsystems, Hecker & Harriman, April 25, 2000: US06055269 (28 worldwide citation)

A method and apparatus for providing equalization for a communication channel is provided. The invention uses edge transition samples, such as those obtained for phase detection in a phase locked loop (PLL) circuit, to determine the amount of equalization to be applied to signals received from a com ...


9
Robert J Bosnyak, Robert J Drost: Method and apparatus for optically aligning integrated circuit devices. Sun Microsystems, Park Vaughan & Fleming, September 27, 2005: US06949406 (24 worldwide citation)

One embodiment of the present invention provides a system that facilitates aligning a first semiconductor die with a second semiconductor die, wherein the first semiconductor die and the second semiconductor die are arranged active face to active face. Note that the active face contains circuitry fo ...


10
Ivan E Sutherland, Robert J Drost, Gary R Lauterbach, Howard L Davidson: Integrated circuit assembly module that supports capacitive communication between semiconductor dies. Sun Microsystems, Park Vaughan & Fleming, March 22, 2005: US06870271 (24 worldwide citation)

One embodiment of the present invention provides an integrated circuit assembly module, including a first semiconductor die and a second semiconductor die, each semiconductor die with an active face upon which active circuitry and signal pads reside and a back face opposite the active face. The firs ...