1
Michael Patrick Chudzik, Robert H Dennard, Rama Divakaruni, Bruce Kenneth Furman, Rajarao Jammy, Chandrasekhar Narayan, Sampath Purushothaman, Joseph F Shepard Jr, Anna Wanda Topol: High density chip carrier with integrated passive devices. Internation Business Machines Corporation, Daniel P Morris Esq, Perman & Green, April 18, 2006: US07030481 (256 worldwide citation)

A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.


2
Michael Patrick Chudzik, Robert H Dennard, Rama Divakaruni, Bruce Kenneth Furman, Rajarao Jammy, Chandrasekhar Narayan, Sampath Purushothaman, Joseph F Shepard Jr, Anna Wanda Topol: High density chip carrier with integrated passive devices. International Business Machines Corporation, Daniel P Morris, Perman & Green, November 8, 2005: US06962872 (243 worldwide citation)

A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.


3
Hussein I Hanafi, Robert H Dennard, Wilfried E Haensch: Threshold voltage roll-off compensation using back-gated MOSFET devices for system high-performance and low standby power. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Wan Yee Cheung Esq, August 8, 2006: US07089515 (109 worldwide citation)

A method for compensating the threshold voltage roll-off using transistors containing back-gates or body nodes is provided. The method includes designing a semiconductor system or chip having a plurality of transistors with a channel length of Lnom. For the present invention, it is assumed that the ...


4
Robert H Dennard, Brian J Greene, Zhibin Ren, Xinlin Wang: Self-aligned well implant for improving short channel effects control, parasitic capacitance, and junction leakage. International Business Machines Corporation, Cantor Colburn, Wenjie Li, August 7, 2012: US08236661 (107 worldwide citation)

A method of forming a self-aligned well implant for a transistor includes forming a patterned gate structure over a substrate, including a gate conductor, a gate dielectric layer and sidewall spacers, the substrate including an undoped semiconductor layer beneath the gate dielectric layer and a dope ...


5
Robert H Dennard, Bernard S Meyerson, Robert Rosenberg: Fabrication of defect free silicon on an insulating substrate. International Business Machines Corporation, Scully Scott Murphy & Presser, July 30, 1996: US05540785 (73 worldwide citation)

A method for fabricating silicon on insulator structures having a dislocation free silicon layer. The method utilizes low temperature UHVCVD to deposit a very heavily doped etch stop layer having a very steep doping profile onto a substrate and a lightly doped active layer onto the etch stop layer. ...


6
Chih Liang Chen, Robert H Dennard, Hussein I Hanafi: CMOS off-chip driver with reduced signal swing and reduced power supply disturbance. International Business Machines Corporation, Scully Scott Murphy & Presser, April 27, 1993: US05206544 (60 worldwide citation)

An off-chip driver circuit which includes a complementary pair of field effect transistor source followers connected in a non-inverting series circuit arrangement. The driver circuit includes an n-channel device to pull the output up to the positive supply less the threshold drop across the device a ...


7
Robert H Dennard, Bernard S Meyerson, Robert Rosenberg: Method of fabricating defect-free silicon on an insulating substrate. International Business Machines Corporation, Scully Scott Murphy & Presser, October 31, 1995: US05462883 (57 worldwide citation)

A method for fabricating silicon on insulator structures having a dislocation free silicon layer. The method utilizes low temperature UHVCVD to deposit a very heavily doped etch stop layer having a very steep doping profile onto a substrate and a lightly doped active layer onto the etch stop layer. ...


8
Paul D Agnello, Stephen W Bedell, Robert H Dennard, Anthony G Domenicucci, Keith E Fogel, Devendra K Sadana: Relaxed, low-defect SGOI for strained Si CMOS applications. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Robert M Trepp Esq, April 15, 2008: US07358166 (40 worldwide citation)

Thermal mixing methods of forming a substantially relaxed and low-defect SGOI substrate material are provided. The methods include a patterning step which is used to form a structure containing at least SiGe islands formed atop a Ge resistant diffusion barrier layer. Patterning of the SiGe layer int ...


9
Robert H Dennard: Low power interface circuit. International Business Machines Corporation, Blaney Harper, David Aker, January 3, 1995: US05378943 (35 worldwide citation)

The interface circuit of the present invention adjusts the signal voltage across a leaking transistor such that the leakage is reduced while also shunting out the adjustment means when the adjustment means impedes the operation of the interface circuit. One embodiment of the present invention is a l ...


10
Wing K Luk, Robert H Dennard: Single cycle read/write/writeback pipeline, full-wordline I/O DRAM architecture with enhanced write and single ended sensing. International Business Machines Corporation, George Sai Halasz, August 29, 2006: US07099216 (33 worldwide citation)

A DRAM is disclosed which includes a single ended bitline structure, a single ended global bitline structure, primary sense amplifiers with data storage and data write-back capability and with capability to decouple from the global bitlines, a full-wordline I/O structure where essentially all memory ...