1
Robert E Cypher: Error detection/correction code which detects and corrects component failure and which provides single bit error correction subsequent to component failure. Sun Microsystems, Lawrence J Merkel, Meyertons Hood Kivlin Kowert & Goetzel P C, December 6, 2005: US06973613 (69 worldwide citation)

A memory controller comprises a check bit encoder circuit and a check/correct circuit. The check bit encoder circuit is coupled to receive a data block to be written to a memory comprising a plurality of memory devices, and is configured to encode the data block with a plurality of check bits to gen ...


2
Robert E Cypher: Memory/Transmission medium failure handling controller and method. Sun Microsystems, Lawrence J Merkel, Meyertons Hood Kivlin Kowert & Goetzel P C, December 13, 2005: US06976194 (68 worldwide citation)

A memory controller may include a check bit encoder circuit and a check/correct circuit. The check bit encoder circuit is coupled to receive a data block to be written to memory, where the memory includes a plurality of memory devices arranged on a plurality of memory modules. Each of the plurality ...


3
Robert E Cypher: Error detection/correction code which detects and corrects a first failing component and optionally a second failing component. Sun Microsystems, Lawrence J Merkel, Meyertons Hood Kivlin Kowert & Goetzel P C, February 7, 2006: US06996766 (39 worldwide citation)

A memory controller includes a check/correct circuit and a data remap circuit. The check/correct circuit is coupled to receive an encoded data block from a memory comprising a plurality of memory devices. The encoded data block includes a plurality of check bits, and the check/correct circuit is con ...


4
Robert E Cypher, Jorge L C Sanz: Hierarchical interconnection network architecture for parallel processing, having interconnections between bit-addressible nodes based on address bit permutations. International Business Machines Corporation, James C Pintner, Joseph J Kaliko, April 30, 1996: US05513371 (37 worldwide citation)

Two new classes of interconnection networks are described. The new classes of interconnection networks are referred to herein as the hierarchical shuffle-exchange (HSE) and hierarchical de Bruijn (HdB) networks. The new HSE and HdB networks are highly regular and scalable and are thus well suited to ...


5
Robert E Cypher: System and method for tolerating communication lane failures. Sun Microsystems, Meyertons Hood Kivlin Kower & Goetzel P C, Stephen J Curran, August 12, 2008: US07412642 (37 worldwide citation)

A system for tolerating communication lane failures includes a transmitter configured to transmit a segment of data, an error detecting code, and redundant information. The system also includes a receiver coupled to the transmitter via a communication link including a plurality of bit lanes. Each bi ...


6
Jehoshua Bruck, Robert E Cypher, Ching Thien Ho: Method and apparatus for tolerating faults in mesh architectures. International Business Machines Corporation, Joseph J Kaliko, Philip E Blair, January 18, 1994: US05280607 (36 worldwide citation)

A method and apparatus are presented for tolerating up to k faults in d-dimensional mesh architectures based on the approach of adding spare components (nodes) and extra links (edges) to a given target mesh where exactly k spare nodes are added and the number of links per node (degree of the mesh) i ...


7
Robert E Cypher, Luis Gravano: Method of packet routing in torus networks with two buffers per edge. International Business Machines Corporation, Philip E Blair, James C Pintner, August 22, 1995: US05444701 (30 worldwide citation)

A method is for routing packets in parallel computers with torus interconnection networks of arbitrary size and dimension having a plurality of nodes, each of which contains at least 2 buffers per edge incident to the node. For each packet which is being routed or which is being injected into the co ...


8
Drew G Doblar, Robert E Cypher: Computer system employing redundant cooling fans. Sun Microsystems, B Noël Kivlin, Meyertons Hood Kivlin Kowert & Goetzel P C, July 27, 2004: US06768640 (29 worldwide citation)

A computer system employing redundant cooling fans. A system includes a first and a second array of circuit boards and a first and a second cooling fan. The two arrays of circuit boards are positioned such that the first array of circuit boards is substantially perpendicular to the second array of c ...


9
Jehoshua Bruck, Robert E Cypher, Ching Tien Ho: Method for generating hierarchical fault-tolerant mesh architectures. International Business Machines Corporation, James C Pintner, Philip E Blair, April 30, 1996: US05513313 (26 worldwide citation)

A method is disclosed, for use with a multiprocessing hardware mesh architecture including nodes and a network of interconnections between the nodes, for defining and implementing a target logical mesh architecture utilizing a given subset of the nodes and the interconnections of the hardware archit ...


10
Robert E Cypher, Shailender Chaudhry, Anders Landin: Method and apparatus for implementing virtual transactional memory using cache line marking. Sun Microsystems, Park Vaughan & Fleming, Anthony P Jones, March 9, 2010: US07676636 (24 worldwide citation)

Embodiments of the present invention implement virtual transactional memory using cache line marking. The system starts by executing a starvation-avoiding transaction for a thread. While executing the starvation-avoiding transaction, the system places starvation-avoiding load-marks on cache lines wh ...