1
Robert C Wong: Method and apparatus for writing operation in SRAM cells employing PFETS pass gates. International Business Machines Corporation, Daryl K Neff, Cantor Colburn, April 15, 2003: US06549453 (46 worldwide citation)

A method for preparing a computer memory cell for a data write operation thereto is disclosed. The memory cell has a cell supply voltage source which is connected at one end to pull-up devices within the memory cell, and is connected at an opposite end to pull-down devices within the memory cell. Th ...


2
Louis L Hsu, Jack A Mandelman, Robert C Wong, Chih Chao Yang: Real-time adaptive SRAM array for high SEU immunity. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Lisa U Jaklitsch Esq, October 16, 2007: US07283410 (44 worldwide citation)

A system and method for automatically adjusting one or more electrical parameters in a memory device, e.g., SRAM arrays. The system and method implements an SRAM sensing sub-array for accelerated collection of fail rate data for use in determining the operating point for optimum tradeoff between sin ...


3
Robert C Wong: CMOS SRAM cell with PFET passgate devices. International Business Machines Corporation, H Daniel Schnurmann, January 22, 2002: US06341083 (27 worldwide citation)

A CMOS SRAM cell provided with PFET devices as passgate transistors is described to reduce the surface area taken by the pull-up and pull-down devices. A six-transistor, single-port SRAM cell is shown to dissipate 75% less power when compared to conventional cells, and its cell stability improved by ...


4
Seiki Ogura, Nivo Rovedo, Robert C Wong: Process for making and programming a flash memory array. International Business Machines Corporation, Peter W Delio & Peterson Peterson, Susan M Murray, July 30, 1996: US05541130 (21 worldwide citation)

A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pa ...


5
Louis L Hsu, Rajiv V Joshi, Robert C Wong: SRAM with improved noise sensitivity. International Business Machines, Louis J Percello, Law Office of Charles W Peterson Jr, November 25, 2003: US06654277 (18 worldwide citation)

A static random access memory (SRAM) with cells in one portion having a higher beta ratio than the remaining cells of the array. In a first portion, cells have a low &bgr; ratio for high performance. A second portion of the array contains SRAM cells with a higher &bgr; ratio that are more stable tha ...


6
Seiki Ogura, Nivo Rovedo, Robert C Wong: Process for making and programming a flash memory array. International Business Machines Corporation, Raymond A DeLio & Peterson Nuzzo, Susan M Murray, August 5, 1997: US05654917 (17 worldwide citation)

A process for fabricating a high density memory array. N-type impurities are implanted in a p-type substrate to form continuous rails of diffusion that have a substantially flat contour. Each rail of diffusion defines a corresponding bit line. Each rail defines the source and drain region of each pa ...


7
Phung T Nguyen, Robert C Wong: One-transistor static random access memory with integrated vertical PNPN device. International Business Machines Corporation, Joseph P Abate, Hoffman Warnick, October 11, 2011: US08035126 (15 worldwide citation)

A one-transistor static random access memory (1T SRAM) device and circuit implementations are disclosed. The 1T SRAM device includes a planar field effect transistor (FET) on the surface of the cell and a vertical PNPN device integrated to one side of the FET. A base of the PNP of the PNPN device is ...


8
Robert C Wong: Adjustable clock chopper/expander circuit. International Business Machines, Richard A Romanchik, June 23, 1992: US05124573 (15 worldwide citation)

A clock chopper/expander circuit 10 includes a reset dominant latch circuit 20 which is set by a CLOCK IN signal 12 and reset by a delayed CLOCK IN signal labelled DELAY 26, provided by an asymmetrical delay circuit 22 which delays the CLOCK IN signal T.sub.D seconds. The delay circuit 22 utilizes a ...


9
Robert C Wong: Semiconductor memory device and array. International Business Machines Corportion, Peter L Michaelson, March 14, 1989: US04813017 (14 worldwide citation)

A memory array fabricated on a silicon substrate consists of memory cells each having two lateral p-n-p load-injector transistors and two vertical n-p-n flip-flop transistors with the p-n-p's being formed in a portion of the substrate which is electrically isolated from portions of the substrate in ...


10
John E Barth Jr, Subramanian S Iyer, Babar A Khan, Robert C Wong: Secure and dense SRAM cells in EDRAM technology. International Business Machines Corporation, Ira D Blecker, McGuire Woods, January 14, 2003: US06507511 (14 worldwide citation)

Addition of capacitance to the storage nodes of static random access memory cells and other types of integrated circuits substantially increases Q