1
Robert B Johnson: High-temperature, low-noise coaxial cable assembly with high strength reinforcement braid. Endevco Corporation, Hamilton Brook Smith & Reynolds, May 25, 1993: US05214243 (123 worldwide citation)

A high-temperature, low-noise coaxial cable assembly with high strength reinforcement braid is depicted and described. The cable assembly has very low self-noise generation and is particularly useful for telemetry and instrumentation purposes. Also, the cable assembly offers a tensile strength about ...


2
Robert B Johnson, Chester M Nibby Jr, Dana Moore: Sequential chip select decode apparatus and method. Honeywell Information Systems, Faith F Driscoll, Nicholas Prasinos, April 6, 1982: US04323965 (73 worldwide citation)

A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem receives as part of e ...


3
Robert B Johnson, Chester M Nibby Jr, Edward R Salas: Identification apparatus for use in a controller to facilitate the diagnosis of faults. Honeywell Information Systems, Faith F Driscoll, Nicholas Prasinos, August 28, 1984: US04468731 (69 worldwide citation)

A data processing system includes a main memory system which couples in common with a central processing unit to a bus for transfer of data between the central processing unit and memory system. The memory system includes a plurality of memory controllers, each of which controls the operation of a n ...


4
Robert B Johnson, Chester M Nibby Jr: Memory controller with queue control apparatus. Honeywell Information Systems, Faith F Driscoll, Nicholas Prasinos, December 28, 1982: US04366538 (62 worldwide citation)

A memory controller couples to a bus and controls a number of memory module units or memory modules. The controller includes a number of queue circuits for processing a variety of different types of memory requests received from a number of command generating units coupled to the bus requiring the c ...


5
Robert B Johnson, Chester M Nibby Jr, Edward R Salas: Memory system with automatic memory configuration. Honeywell Information Systems, Faith F Driscoll, Nicholas Prasinos, March 26, 1985: US04507730 (57 worldwide citation)

A memory system includes a plurality of memory controllers which connect to a common bus. Each memory controller includes reconfiguration apparatus which enables the controller when faulty to be switched off line and another controller to be substituted in its place so as to maintain system memory c ...


6
Hugh B Morse, Robert B Johnson: Display carton and blank therefor. Helmut E W Masch, Phillips Moore Weissenberger Lempio & Majestic, November 15, 1977: US04058206 (51 worldwide citation)

A display carton comprises a one-piece blank cut and scored to form vertically disposed front, back and side panels and horizontally disposed top and bottom panels. A vertically disposed separate partition is further disposed intermediate the side panels and is attached to the front, back and bottom ...


7
Edward R Salas, Edwin P Fisher, Robert B Johnson, Chester M Nibby Jr, Daniel A Boudreau: Memory identification apparatus and method. Honeywell Information Systems, Faith F Driscoll, Nicholas Prasinos, October 1, 1985: US04545010 (45 worldwide citation)

A memory system includes at least one or more memory module boards identical in construction and a single computer board containing the control circuits for controlling memory operations. Each board plugs into the main board and includes a memory section having a number of rows of memory chips and a ...


8
Robert B Johnson, Chester M Nibby Jr: Soft error rewrite control system. Honeywell Information Systems, Faith F Driscoll, Nicholas Prasinos, January 18, 1983: US04369510 (42 worldwide citation)

Refresh and initialize counter circuits included within a dynamic memory system are supplemented with additional counter control circuits for synchronizing them from the same timing source which drives the refresh and initialize counter circuits. The counter control circuits count in accordance with ...


9
Robert B Johnson, Chester M Nibby Jr: Method and apparatus for testing and verifying the operation of error control apparatus within a memory. Honeywell Information Systems, Faith F Driscoll, Nicholas Prasinos, November 16, 1982: US04359771 (40 worldwide citation)

Soft error rewrite control apparatus is included within a memory system for rendering the semiconductor memory modules less susceptible to single bit errors produced by alpha particles and other system disturbances. During a number of successive memory cycles occurring at a predetermined rate, the s ...


10
George J Barlow, Chester M Nibby Jr, Robert B Johnson: Pause apparatus for a memory controller with interleaved queuing apparatus. Honeywell Information Systems, Faith F Driscoll, John S Solakian, December 10, 1985: US04558429 (32 worldwide citation)

A data processing system includes a plurality of memory command generating units which connect to a common bus network with a number of memory subsystems. Each subsystem includes a controller which controls the operation of a number of memory module units and includes a number of queue circuits for ...