1
Michael T Wisor, Rita M O Brien: Power management system distinguishing between primary and secondary system activity. Advanced Micro Devices, B Noel Kivlin, April 23, 1996: US05511203 (133 worldwide citation)

A power management unit is provided that includes several states, each of which is associated with a different power management mode. Transitions between the states of the power management unit are dependent upon the type of activities detected. Upon reset of the computer system, the power managemen ...


2
Douglas D Gephardt, James R MacDonald, Rita M O Brien: Power management architecture including a power management messaging bus for conveying an encoded activity signal for optimal flexibility. Advanced Micro Devices, B Noel Kivlin, February 20, 1996: US05493684 (130 worldwide citation)

An integrated processor is provided that includes a CPU core coupled to a variety of on-chip peripheral devices such as a DMA controller, an interrupt controller, and a timer. The integrated processor further includes a power management message unit coupled to the DMA controller, interrupt controlle ...


3
Rita M O Brien, Michael T Wisor: Power management control technique for timer tick activity within an interrupt driven computer system. Advanced Micro Devices, B Noel Kivlin, Conley Rose & Tayon, September 2, 1997: US05664205 (47 worldwide citation)

A power management unit is provided that monitors various portions of a computer system and causes a reduction in the frequencies of the CPU clock signal and the system clock signal during a power conserving state. The power management unit includes a programmable counter for allowing the system des ...


4
Michael T Wisor, Rita M O Brien: Power management unit including software configurable state register and time-out counters for protecting against misbehaved software. Advanced Micro Devices, B Noel Kivlin, April 2, 1996: US05504910 (41 worldwide citation)

A power management unit including a set of time-out counters and a software configurable state register is provided for managing power consumption within a computer system. Depending upon the state of the power management unit, a power control unit and a clock control unit are configured such that p ...


5
Michael T Wisor, Rita M O Brien: Disable technique employed during low battery conditions within a portable computer system. Advanced Micro Devices, Conley Rose & Tayon, August 15, 1995: US05442794 (39 worldwide citation)

A computer system is provided that employs a disable technique which warns the user of a low battery condition when the user attempts to power-on the computer, and which prevents power from being applied to a primary portion of the computer system. A battery monitor is included for monitoring the vo ...


6
Rita M O Brien: Sub-bus activity detection technique for power management within a computer system. Advanced Micro Devices, B Noel Kivlin, Conley Rose & Tayon P C, January 21, 1997: US05596756 (25 worldwide citation)

The computer system includes an integrated processor coupled to a power management unit and at least one peripheral device. The integrated processor includes a bus interface unit that provides an interface to a high performance peripheral interconnect bus with multiplexed address/data lines. The per ...


7
Rita M O Brien: System oscillator gating technique for power management within a computer system. Advanced Micro Devices, B Noel Kivlin, Conley Rose & Tayon P C, May 6, 1997: US05628020 (16 worldwide citation)

A system oscillator gating technique is provided for a power management unit of a computer system for controlling the application of power to a system oscillator. An output signal from the power management unit is provided to turn off the external system oscillator when the computer system is in a p ...


8
Rita M O Brien: Heuristic bus access arbiter. Advanced Micro Devices, Foley & Lardner, August 18, 1998: US05796961 (15 worldwide citation)

An arbiter connects a plurality of devices to a bus. The arbiter determines priority among the devices based on the relative need of the devices. Relative need is determined for each device based on the fullness of a buffer, such as a first-in first-out buffer, corresponding to each device. A gauge ...


9
Rita M O Brien: System and method for controlling a peripheral bus clock signal during a reduced power mode. Advanced Micro Devices, B Noel Conley Rose & Tayon Kivlin, May 6, 1997: US05628019 (14 worldwide citation)

A system and method for controlling a peripheral bus clock signal through a slave device are provided that accommodate a power conservation scheme in which a peripheral bus clock signal may be stopped, for example, by a power management unit or other central resource. Upon system reset, the BIOS boo ...


10
Rita M O Brien: Sytem and method for merging disk change data from a floppy disk controller with data relating to an IDE drive controller. Advanced Micro Devices, B Noel Kivlin, July 9, 1996: US05535419 (13 worldwide citation)

A system is disclosed for merging data from two separate registers at different locations in a computer system. A floppy drive controller is provided as part of a companion chip located separately from an IDE drive controller. Both controllers include a data register with the same address to make th ...