1
Osama Khouri, Rino Micheloni, Ilaria Motta, Andrea Sacco, Guido Torelli: Capacitive boosting circuit for the regulation of the word line reading voltage in non-volatile memories. STMicroelectronics S r l, Theodore E Galanthay, E Russell Tarleton, Seed IP Law Group PLLC, July 10, 2001: US06259635 (73 worldwide citation)

A circuit for the regulation of the word line voltage in a memory, comprising a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more word lines of the memory when the one or more word lines are being selected. The circuit includes a voltage boosting circui ...


2
Osama Khouri, Rino Micheloni, Ilaria Motta, Andrea Sacco, Guido Torelli: Capacitive compensation circuit for the regulation of the word line reading voltage in non-volatile memories. STMicroelectronics S r l, Theodore E Galanthay, E Russell Tarleton, Seed IP Law Group PLLC, July 10, 2001: US06259632 (71 worldwide citation)

Circuit for the regulation of the word line voltage in a memory, including a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more word lines of the memory when said one or more word lines are being selected, and charge accumulation means that are selective ...


3
Rino Micheloni, Giovanni Campardo: Method for storing and reading data in a multilevel nonvolatile memory. STMicroelectronics S r l, Lisa K Jorgenson, Robert Iannucci, Seed IP Law Group PLLC, November 11, 2003: US06646913 (68 worldwide citation)

The data management method applies to a multilevel nonvolatile memory device having a memory array formed by a plurality of memory cells. Each of the memory cells stores a number of bits that is not an integer power of two, for example three. In this way, one data byte is stored in a non-integer num ...


4
Giovanni Campardo, Rino Micheloni, Marco Maccarrone: Circuit and method for generating a read reference signal for nonvolatile memory cells. SGS Thomson Microelectronics S r l, David V Carlson, Bryan A Seed and Berry Santarelli, September 8, 1998: US05805500 (65 worldwide citation)

The current flowing through a cell to be read, forming part of a nonvolatile memory array and presenting a characteristic with a predetermined slope, is amplified N times and compared with a reference current presenting a two portion characteristic: a first portion extending between a predetermined ...


5
Stefano Gregori, Rino Micheloni, Andrea Pierin, Osama Khouri, Guido Torelli: Method for programming nonvolatile memory cells with program and verify algorithm using a staircase voltage with varying step amplitude. STMicroelectronics S r l, Lisa K Jorgenson, Harold H Bennett II, Seed IP Law Group PLLC, September 7, 2004: US06788579 (65 worldwide citation)

A method for programming a nonvolatile memory cell envisages applying in succession, to the gate terminal of the memory cell, a first and a second programming pulse trains with pulse amplitude increasing in staircase fashion, in which the amplitude increment between one pulse and the next in the fir ...


6
Rino Micheloni, Alessia Marelli, Peter Z Onufryk, Christopher I W Norrie: Nonvolatile memory controller with error detection for concatenated error correction codes. PMC Sierra US, Kenneth Glass, Stanley J Pawlik, Glass & Associates, December 31, 2013: US08621318 (49 worldwide citation)

A nonvolatile memory controller to recover encoded data by performing a hard-decision inner error correction code decoding and an outer error correction code decoding of the data decoded using the hard-decision inner error correction code decoding and then determining if the encoded data has been su ...


7
Rino Micheloni, Giovanni Campardo, Atsushi Ohba, Marcello Carrera: Row decoder for a nonvolatile memory with capability of selectively biasing word lines to positive or negative voltages. STMicroelectronics S r l, Mitsubishi Electric Corporation, Lisa K Jorgenson, David V Carlson, SEED IP Law Group PLLC, March 12, 2002: US06356481 (36 worldwide citation)

The row decoder includes, for each word line of the memory, a respective biasing circuit receiving at the input a row selection signal switching, in preset operating conditions, between a supply voltage and a ground voltage and supplying at the output a biasing signal for the respective word line sw ...


8
Rino Micheloni, Giovanni Campardo, Salvatrice Scommegna: METHOD FOR ERASING AN ELECTRICALLY ERASABLE NONVOLATILE MEMORY DEVICE, IN PARTICULAR AN EEPROM-FLASH MEMORY DEVICE, AND AN ELECTRICALLY ERASABLE NONVOLATILE MEMORY DEVICE, IN PARTICULAR AN EEPROM-FLASH MEMORY DEVICE. STMicroelectronics S r l, Lisa K Jorgenson, Dennis M de Guzman, Seed IP Law Group PLLC, March 22, 2005: US06871258 (32 worldwide citation)

Described herein is an erase method for an electrically erasable nonvolatile memory device, in particular an EEPROM-FLASH nonvolatile memory device, comprising a memory array formed by a plurality of memory cells arranged in rows and columns and grouped in sectors each formed by a plurality of subse ...


9
Rino Micheloni, Alessia Marelli, Peter Z Onufryk, Christopher I W Norrie: Nonvolatile memory controller with concatenated error correction codes. PMC Sierra US, Kenneth Glass, Molly Sauter, Glass & Associates, February 18, 2014: US08656257 (28 worldwide citation)

A nonvolatile memory controller may recover encoded data using the outer error correction code of the encoded data if it is determined that a correction capacity of the outer error correction code is not exceeded. Alternatively, the nonvolatile memory controller may recover the encoded data using th ...


10
Rino Micheloni, Luca Crippa, Alessia Marelli: Error correction code technique for improving read stress endurance. PMC Sierra US, Kenneth Glass, Stanley J Pawlik, Glass & Associates, April 8, 2014: US08694855 (27 worldwide citation)

A data storage device reads a data unit from a memory page, detects a number of data bit errors in the data unit, and generates a bit error indicator identifying bit indexes of the data bit errors in the data unit. The data storage device reads the data unit from the memory page once again and gener ...