1
Michael E Flynn, Scott Arnold, Stephen J DeLaHunt, Tryggve Fossum, Ricky C Hetherington, David J Webb: Scheme for insuring data consistency between a plurality of cache memories and the main memory in a multi-processor system. Digital Equipment Corporation, Arnold White & Durkee, June 22, 1993: US05222224 (110 worldwide citation)

A method for insuring data consistency between a plurality of individual processor cache memories and the main memory in a multi-processor computer system is provided which is capable of (1) detecting when one of a set of predefined data inconsistency states occurs as a data transaction request is b ...


2
Sharad Mehrotra, Ricky C Hetherington, Michelle L Wong: Apparatus and method for handling multiple mergeable misses in a non-blocking cache. Sun Microsystems, Stuart T Langley, William J Hogan & HartsonLLP Kubida, November 7, 2000: US06145054 (99 worldwide citation)

A method and apparatus for merging multiple misses to a multi-level cache is provided to improve the performance of the cache. A first and second non-blocking cache are each provided with miss queues storing entries corresponding to access requests not serviced by the respective caches. The first an ...


3
Douglas J Burns, David M Fenwick, Ricky C Hetherington: Delay compensated signal propagation. Digital Equipment Corporation, Dirk Brinkman, Ronald Hudgens, Arthur Fisher, December 12, 1995: US05475690 (96 worldwide citation)

In a computer system, digital signals are transmitted from an output register, propagated along a first signaling path, and received by an input register. The signaling path including an address buffer, a cache memory, a main memory, and an interconnect network. The effects of the intrinsic delays e ...


4
Tryggve Fossum, Ricky C Hetherington, David B Fite Jr, Dwight P Manley, Francis X McKeen, John E Murray: Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements. Digital Equipment Corporation, Arnold White & Durkee, December 19, 1989: US04888679 (95 worldwide citation)

A main memory and cache suitable for scalar processing are used in connection with a vector processor by issuing prefetch requests in response to the recognition of a vector load instruction. A respective prefetch request is issued for each block containing an element of the vector to be loaded from ...


5
David A Webb Jr, Ricky C Hetherington, John E Murray, Tryggve Fossum, Dwight P Manley: Method and apparatus for ordering and queueing multiple memory requests. Digital Equipment Corporation, Arnold White & Durkee, June 22, 1993: US05222223 (81 worldwide citation)

In a pipelined computer system 10, memory access functions (requests) are simultaneously generated from a plurality of different locations. These multiple requests are passed through a multiplexer 50 according to a prioritization scheme based upon the operational proximity of the request to the inst ...


6
David A Webb Jr, David B Fite, Ricky C Hetherington, Francis X McKeen, Mark A Firstenberg, John E Murray, Dwight P Manley, Ronald M Salett, Tryggve Fossum: System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer. Digital Equipment Corporation, Arnold White & Durkee, January 15, 1991: US04985825 (77 worldwide citation)

A technique for processing memory access exceptions along with pre-fetched instructions in a pipelined instruction processing computer system is based upon the concept of pipelining exception information along with other parts of the instruction being executed. In response to the detection of access ...


7
David B Fite, Tryggve Fossum, Ricky C Hetherington, John E Murray, Jr David A Webb: Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system. Digital Equipment Corporation, Arnold White & Durkee, June 23, 1992: US05125083 (73 worldwide citation)

An operand processing unit delivers a specified address and at least one read/write signal in response to an instruction being a source of destination operand, and delivers the source operand to an execution unit in response to completion of the preprocessing. The execution unit receives the source ...


8
Ramesh Panwar, Ricky C Hetherington: Apparatus for dynamically reconfiguring a processor. Sun Microsystems, Philip J McKay, Gunnison McKay & Hodgson L, May 29, 2001: US06240502 (72 worldwide citation)

A method and apparatus for dynamically reconfiguring a processor involves placing the processor in a first configuration having a first number (m) of strands while the coded instructions comprise instructions from a number (m) threads. The instructions in each of the m threads are executed on one of ...


9
Ricky C Hetherington, Francis X McKeen, Joseph D Marci, Tryggve Fossum, Joel S Emer: Integrated circuit chip having primary and secondary random access memories for a hierarchical cache. Digital Equipment Corporation, Arnold White & Durkee, February 8, 1994: US05285323 (61 worldwide citation)

A hierarchical cache memory includes a high-speed primary cache memory and a lower speed secondary cache memory of greater storage capacity than the primary cache memory. To manage a huge number of data lines interconnecting the primary and secondary cache memories, the hierarchical cache memory is ...


10
Thomas M Wicki, Meera Kasinathan, Fong Pong, Ricky C Hetherington: Speculative cache line write backs to avoid hotspots. Sun Microsystems, Philp McKay, Gunnison McKay & Hodgson, September 12, 2000: US06119205 (54 worldwide citation)

A cache system including a data cache memory comprising a plurality of cache lines. A tag store has an entry representing each line in the cache memory where each entry comprises tag information for accessing the data cache. The tag information includes state information indicating whether the repre ...