1
Richard W Jarvis: Product wafer yield prediction method employing a unit cell approach. Advanced Micro Devices, Kevin L Conley Rose & Tayon Daffer, June 30, 1998: US05773315 (105 worldwide citation)

A method is presented for determining a predicted yield value for a silicon wafer subjected to a wafer fabrication process. The wafer fabrication process forms multiple integrated circuits (i.e., chips) upon a surface of the wafer. A unit cell region is chosen on the surface of the wafer and within ...


2
Richard W Jarvis, Iraj Emami, John L Nistler, Michael G McIntyre: Multipurpose defect test structure with switchable voltage contrast capability and method of use. Advanced Micro Devices, Kevin L Daffer, Conley Rose & Tayon P C, October 2, 2001: US06297644 (89 worldwide citation)

A test structure which includes alternating grounded and floating conductive lines may be used to test the formation of conductive features on an integrated circuit topography. During irradiation of the conductive lines from an electron source, the grounded conductive lines will appear darker than t ...


3
Richard W Jarvis, Iraj Emami, Charles E May: Drop-in test structure and methodology for characterizing an integrated circuit process flow and topography. Advanced Micro Devices, Kevin L Daffer, Conley Rose & Tayon P C, September 17, 2002: US06452412 (87 worldwide citation)

A drop-in test structure fabricated upon a production integrated circuit elevational profile and a method for using the drop-in test structure for characterizing an integrated circuit production methodology are described. The test structure may be fabricated upon an integrated circuit elevational pr ...


4
Richard W Jarvis, Michael G McIntyre: Integrated defect monitor structures for conductive features on a semiconductor topography and method of use. Advanced Micro Devices, Kevin L Daffer, Conley Rose & Tayon P C, March 26, 2002: US06362634 (21 worldwide citation)

A test structure which includes a first conductive feature layer and a second conductive feature layer is described. The first conductive feature layer includes a first conductive line. The second conductive feature layer includes a second conductive line. A daisy chain conductive feature is also in ...


5
Richard W Jarvis, Iraj Emami, Alan B Berezin: Semiconductor test structure with intentional partial defects and method of use. Advanced Micro Devices, Kevin L Daffer, Conley Rose & Tayon P C, July 31, 2001: US06268717 (18 worldwide citation)

A test structure which includes alternating grounded and floating conductive lines may be used to test the formation of conductive features on an integrated circuit topography. A number of intentional partial defects may be formed at predetermined locations along the test structure. During irradiati ...


6
Richard W Jarvis: Test structure and methodology for characterizing etching in an integrated circuit fabrication process. Advanced Micro Devices, Kevin L Daffer, Conley Rose & Tayon P C, July 10, 2001: US06258437 (8 worldwide citation)

A test structure for characterizing etching procedures used in integrated circuit fabrication processes and a method for using the test structure are described. The test structure includes a contrast layer, a simulated substrate, and a pattern layer arranged in order upon a substrate. The simulated ...


7
Richard W Jarvis: Micro-void detection. Advanced Micro Devices, July 3, 2001: US06253621 (6 worldwide citation)

According to an example embodiment of the present invention, a semiconductor device having conductive structure is analyzed using acoustic energy. Acoustic energy is generated in the device, and a resulting acoustic wave is detected. Using the detected wave, an index of refraction of a portion of th ...


8
Richard W Jarvis: Test structure and methodology for characterizing ion implantation in an integrated circuit fabrication process. Advanced Micro Devices, Kevin L Daffer, Conley Rose & Tayon P C, August 6, 2002: US06429452 (6 worldwide citation)

A test structure for characterizing ion implantation procedures used in integrated circuit fabrication processes and a method for using the test structure are described. The test structure includes a first dielectric layer, a patterned polysilicon layer, and a second dielectric layer arranged in ord ...


9
Richard W Jarvis, Iraj Emami, Charles E May: Drop-in test structure and abbreviated integrated circuit process flow for characterizing production integrated circuit process flow, topography, and equipment. Advanced Micro Devices, Kevin L Daffer, Conley Rose & Tayon P C, September 25, 2001: US06294397 (5 worldwide citation)

A drop-in test structure fabricated upon a virtual integrated circuit elevational profile and a method for using the drop-in test structure for characterizing an integrated circuit production methodology and integrated circuit fabrication equipment are described. According to an embodiment, the test ...