1
Andrew H Mason, Judith S Hall, Paul T Robinson, Richard T Witek: Translation buffer for virtual machines with address space match. Digital Equipment Corporation, Arnold White & Durkee, June 7, 1994: US05319760 (161 worldwide citation)

A central processing unit (CPU) executing a virtual memory management system employs a translation buffer for caching recently used page table entries. When more than one process is executing on the CPU, the translation buffer is usually flushed when a context switch is made, even though some of the ...


2
Richard L Sites, Richard T Witek: Ensuring data integrity by locked-load and conditional-store operations in a multiprocessor system. Digital Equipment Corporation, Arnold White & Durkee, March 9, 1993: US05193167 (102 worldwide citation)

A high performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte mani ...


3
Richard T Witek, Douglas D Williams, Timothy J Stanley, David M Fenwick, Douglas J Burns, Rebecca L Stamm, Richard Heye: Pipeline having an integral cache which processes cache misses and loads data in parallel. Digital Equipment Corporation, Kenyon & Kenyon, September 15, 1992: US05148536 (96 worldwide citation)

A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained ind ...


4
Richard Lee Sites, Richard T Witek: Branch prediction in high-performance processor. Digital Equipment Corporation, Hamilton Brook Smith & Reynolds P C, June 13, 2000: US06076158 (96 worldwide citation)

A CPU of the RISC type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes limited to register-to-register operations and register load/store operations. Byte manipulation instructions include the facility for doing in-register by ...


5
Richard L Sites, Richard T Witek: Virtual to physical address translation scheme with granularity hint for identifying subsequent pages to be accessed. Digital Equipment Corporation, Arthur W Fisher, Denis G Maloney, Lindsay G McGuinness, September 26, 1995: US05454091 (87 worldwide citation)

A high-performance central processing unit (CPU) of the reduced instruction set (RISC) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/s ...


6
David N Cutler, David A Orbits, Dileep Bhandarkar, Wayne Cardoza, Richard T Witek: Apparatus and method for recovering from missing page faults in vector data processing operations. Digital Equipment Corporation, Fish & Richardson, November 5, 1991: US05063497 (76 worldwide citation)

In a data processing system employing virtual memory techniques and capable of performing a plurality of overlapping scalar and vector data processing operations, apparatus and method are provided to allow continuation of program execution after one or more vector load/store instructions, which refe ...


7
Richard L Sites, Richard T Witek: Byte-compare operation for high-performance processor. Digital Equipment Corporation, Denis G Maloney, Arthur W Fisher, October 22, 1996: US05568624 (71 worldwide citation)

A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte mani ...


8
Richard T Witek, Douglas D Williams, Timothy J Stanley, David M Fenwick, Douglas J Burns, Rebecca L Stamm, Richard Heye: Pipeline utilizing an integral cache for transferring data to and from a register. Digital Equipment Corporation, Denis G Maloney, Arthur W Fisher, July 4, 1995: US05430888 (52 worldwide citation)

A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained ind ...


9
Scott G Robinson, Richard L Sites, Richard T Witek: System and method for preserving instruction state-atomicity for translated program. Digital Equipment Corporation, David A Dagg, Denis G Maloney, Arthur W Fisher, June 3, 1997: US05636366 (40 worldwide citation)

A system or method is provided for translating a first program code to a second program code and for executing the second program code while preserving instruction state-atomicity of the first code. The first program code is executable on a computer having a first architecture adapted to a first ins ...


10
David N Cutler, David A Orbits, Dileep Bhandarkar, Wayne Cardoza, Richard T Witek: Providing a data processor with a user-mode accessible mode of operations in which the processor performs processing operations without interruption. Digital Equipment Corporation, Fish & Richardson, June 8, 1993: US05218712 (37 worldwide citation)

In a data processing system employing microcode techniques, complex sequences of microinstructions can be initiated by application of a single macroinstruction. These complex sequences of microinstructions are typically noninterruptible and therefore the execution of a macroinstruction is atomic (i. ...