1
James A Gasbarro, Mark A Horowitz, Richard M Barth, Winston K M Lee, Wingyu Leung, Paul M Farmwald: Method and circuitry for minimizing clock-data skew in a bus system. Rambus, Blakely Sokoloff Taylor & Zafman, July 11, 1995: US05432823 (327 worldwide citation)

A bus system is described that minimizes clock-data skew. The bus system includes a data bus, a clockline and synchronization circuitry. The clockline has two clockline segments. Each clockline segment extends the entire length of the data bus and is joined to the other clockline segment by a turnar ...


2
Mark A Horowitz, Richard M Barth, Craig E Hampel, Alfredo Moncayo, Kevin S Donnelly, Jared L Zerbe: Apparatus and method for topography dependent signaling. Rambus, November 20, 2001: US06321282 (226 worldwide citation)

Bus communications are optimized by adjusting signal characteristics in accordance with one or more topography dependent parameters. In a bus transmitter, a transmit signal characteristic is adjusted in accordance with a topography dependent parameter. A port in the bus transmitter receives the topo ...


3
Richard M Barth, Frederick A Ware, Donald C Stark, Craig E Hampel, Paul G Davis, Abhijit M Abhyankar, James A Gasbarro, David Nguyen, Thomas J Holman, Andrew V Anderson, Peter D MacWilliams: High performance cost optimized memory with delayed memory writes. Rambus Incorporated, Intel Corporation, Pennie & Edmonds, June 13, 2000: US06075730 (134 worldwide citation)

A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core wr ...


4
Frederick A Ware, James A Gasbarro, John B Dillon, Matthew M Griffin, Richard M Barth, Mark A Horowitz: Method and apparatus for power control in devices. Rambus, Blakely Sokoloff Taylor & Zafman, August 9, 1994: US05337285 (122 worldwide citation)

A power control circuit to minimize power consumption of CMOS circuits by disabling/enabling the clock input to the CMOS circuit. A phase locked loop (PLL) or delay locked loop (DLL) drives a capacitive load of the component and a dummy load comparable to the component load. A standby latch is provi ...


5
Ely K Tsern, Richard M Barth, Craig E Hampel, Donald C Stark: Power control system for synchronous memory device. Rambus, Gary S Williams, Pennie & Edmonds, March 2, 2004: US06701446 (117 worldwide citation)

A memory device with multiple clock domains. Separate clocks to different portions of the control circuitry create different clock domains. The different domains are sequentially turned on as needed to limit the power consumed. The turn on time of the domains is overlapped with the latency for the m ...


6
Richard M Barth, Ely K Tsern, Craig E Hampel, Frederick A Ware, Todd W Bystrom, Bradley A May, Paul G Davis: Method and apparatus for initializing dynamic random access memory (DRAM) devices by levelizing a read domain. Rambus, Blakely Sokoloff Taylor & Zafman, November 28, 2000: US06154821 (115 worldwide citation)

A method and apparatus for initializing dynamic random access memory (DRAM) devices is provided wherein a channel is levelized by determining the response time of each of a number of DRAM devices coupled to a bus. Determining the response time for a DRAM device comprises writing logic ones to a memo ...


7
Ely K Tsern, Thomas J Holman, Richard M Barth, Andrew V Anderson, Paul G Davis, Craig E Hampel, Donald C Stark, Abhijit M Abhyankar: Memory device and system including a low power interface. Intel Corporation, Rambus, Pennie & Edmonds, April 23, 2002: US06378018 (113 worldwide citation)

A memory system includes an interconnect structure with a high speed channel and a low speed channel. A memory device with interface circuitry is coupled to the interconnect structure. The interface circuitry includes a high power interface for coupling to the high speed channel and a low power inte ...


8
Frederick A Ware, John B Dillon, Richard M Barth, Billy W Garrett Jr, John G Atwood Jr, Michael P Farmwald: Dynamic random access memory system. Rambus, Blakely Sokoloff Taylor & Zafman, July 4, 1995: US05430676 (107 worldwide citation)

As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to th ...


9
Billy Wayne Garrett Jr, Frederick Abbott Ware, Craig E Hampel, Richard M Barth, Don Stark, Abhijit Mukund Abhyankar, Catherine Yuhjung Chen, Thomas J Sheffler, Ely K Tsern, Steven Cameron Woo: Memory module with offset data lines and bit line swizzle configuration. Rambus, Morgan Lewis & Bockius, January 4, 2005: US06839266 (94 worldwide citation)

A memory module includes an array of N memory devices, each memory device having M data pins, where N is greater than M, and M and N are positive integers; and N bit lines traversing the array of N memory devices, such that each one of the N bit lines is connected to M of the N memory devices.


10
Richard M Barth, Frederick A Ware, Donald C Stark, Craig E Hampel, Paul G Davis, Abhijit M Abhyankar, James A Gasbarro, David Nguyen: High performance cost optimized memory. Rambus Incorporated, Pennie & Edmonds, June 4, 2002: US06401167 (94 worldwide citation)

A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals fro ...