1
Rebecca L Stamm, R Iris Bahar, Michael Callander, Linda Chao, Derrick R Meyer, Douglas Sanders, Richard L Sites, Raymond Strouble, Nicholas Wade: Error transition mode for multi-processor system. Digital Equipment Corporation, Arnold White & Durkee, October 13, 1992: US05155843 (106 worldwide citation)

A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queueing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth ...


2
Richard L Sites, Richard T Witek: Ensuring data integrity by locked-load and conditional-store operations in a multiprocessor system. Digital Equipment Corporation, Arnold White & Durkee, March 9, 1993: US05193167 (102 worldwide citation)

A high performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte mani ...


3
Scott G Robinson, Richard L Sites: System and method for preserving instruction granularity when translating program code from a computer having a first architecture to a computer having a second reduced architecture during the occurrence of interrupts due to asynchronous events. Digital Equipment Corporation, Albert P Cefalo, Barry N Young, April 26, 1994: US05307504 (94 worldwide citation)

A computer program of complex instruction set code (CISC) is translated to produce a program of reduced instruction set code (RISC). Each CISC instruction is translated into a sequence of RISC instructions. The sequence includes in order four groups of instructions. The first group includes instruct ...


4
James A Farrell, Richard L Sites: Configurable set associative cache with decoded data element enable lines. Digital Equipment Corporation, Cesari and McKenna, May 7, 1991: US05014195 (89 worldwide citation)

A set associative cache using decoded data element select lines which can be selectively configured to provide different data sets arrangements. The cache includes a tag array, a number of tag comparators corresponding to the maximum possible number of sets, a data element select logic circuit, and ...


5
Richard L Sites, Richard T Witek: Virtual to physical address translation scheme with granularity hint for identifying subsequent pages to be accessed. Digital Equipment Corporation, Arthur W Fisher, Denis G Maloney, Lindsay G McGuinness, September 26, 1995: US05454091 (87 worldwide citation)

A high-performance central processing unit (CPU) of the reduced instruction set (RISC) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/s ...


6
Richard L Sites: Alternate and iterative analysis of computer programs for locating translatable code by resolving callbacks and other conflicting mutual dependencies. Digital Equipment Corporation, Arnold White & Durkee, May 31, 1994: US05317740 (83 worldwide citation)

Information about the effects of calling each entry point in a program and information about external calls made by the program are recorded in an image information file. In addition to the addresses of the entry points and call destinations, the information may include any callback parameters and r ...


7
Monika Hildegard Henzinger, Shun Tak Albert Leung, Richard L Sites, Mark T Vandevoorde, William Edward Weihl: Method for identifying reasons for dynamic stall cycles during the execution of a program. Digital Equipment Corporation, January 5, 1999: US05857097 (83 worldwide citation)

In a computerized method, performance data collected while a computer system executed instructions of a program are analyzed. The method collects performance data while executing the program. The performance data includes sample counts of instructions executed. The program is analyzed to determine c ...


8
Lance M Berc, Sanjay Ghemawat, Monika H Henzinger, Richard L Sites, Carl A Waldspurger, William E Weihl: High frequency sampling of processor performance counters. Digital Equipment Corporation, Dirk Brinkman, August 18, 1998: US05796939 (79 worldwide citation)

In a computer system, an apparatus is configured to collect performance data of a computer system including a plurality of processors for concurrently executing instructions of a program. A plurality of performance counters are coupled to each processor. The performance counters store performance da ...


9
Richard L Sites: Use of stack depth to identify machine code mistakes. Digital Equipment Corporation, Gary E Ross, Arthur W Fisher, September 12, 1995: US05450575 (73 worldwide citation)

A code translator, constructed similar to a compiler, accepts as an input to be translated the assembly code written for one architecture (e.g., VAX), and produces as an output object code for a different machine architecture (e.g., RISC). The input code is converted into an intermediate language, a ...


10
Richard L Sites, Richard T Witek: Byte-compare operation for high-performance processor. Digital Equipment Corporation, Denis G Maloney, Arthur W Fisher, October 22, 1996: US05568624 (71 worldwide citation)

A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte mani ...