1
Pankaj Dixit, Jack Sliwa, Richard K Klein, Craig S Sander, Mohammad Farnaam: Contact plug and interconnect employing a barrier lining and a backfilled conductor material. Advanced Micro Devices, Ashen Golant Martin & Seldon, November 28, 1989: US04884123 (172 worldwide citation)

A stable, low resistance contact is formed in a contact hole (16) through an insulating layer (14), e.g., silicon dioxide, formed on a surface of a semiconductor substrate (12), e.g., silicon, to a portion of a doped region (10) in said semiconductor surface. The contact comprises (a) an adhesion an ...


2
Pankaj Dixit, Jack Sliwa, Richard K Klein, Craig S Sander, Mohammad Farnaam: Contact plug and interconnect employing a barrier lining and a backfilled conductor material. Advanced Micro Devices, David W Collins, October 2, 1990: US04960732 (98 worldwide citation)

A stable, low resistance contact is formed in a contact hole (16) through an insulating layer (14), e.g., silicon dioxide, formed on a surface of a semiconductor substrate (12), e.g., silicon, to a portion of a doped region (10) in said semiconductor surface. The contact comprises (a) an adhesion an ...


3
Raymond T Lee, Richard K Klein: Method for eliminating window mask process in the fabrication of a semiconductor wafer when chemical-mechanical polish planarization is used. Advanced Micro Devices, Fliesler Dubb Meyer & Lovejoy, May 6, 1997: US05627110 (32 worldwide citation)

A method of fabricating semiconductor devices which eliminates the need to use additional window mask process to expose topographical marks, such as alignment targets, on a wafer when chemical-mechanical polish planarization technique are used to substantially planarize the surface of the wafer prio ...


4
Richard K Klein, Darrell Erb, Steven Avanzino, Robin Cheung, Scott Luning, Bryan Tracy, Subhash Gupta, Ming Ren Lin: Copper reservoir for reducing electromigration effects associated with a conductive via in a semiconductor device. Advanced Micro Devices, Foley & Lardner, June 23, 1998: US05770519 (25 worldwide citation)

A multilayer semiconductor structure includes a conductive via. The conductive via includes a reservoir of metal having a high resistance to electromigration. The reservoir is made from a conformal layer of copper, or gold deposited over the via to form a copper, or gold plug located in the via. A b ...


5
Tat C Choi, Richard K Klein, Craig S Sander: Triple-poly 4T static ram cell with two independent transistor gates. Advanced Micro Devices, Salzman & Levy, August 21, 1990: US04951112 (24 worldwide citation)

A 4T static RAM cell (10) comprising a flip-flop with two pull-down transistors (18, 20) and two pass-gate transistors (12, 14) is fabaricated employing two separate gate oxide formations (74, 76) and associated separate polysilicon depositions (52a -b, 56). Two reduced area contacts (58, 60) connec ...


6
Richard K Klein, Asim A Selcuk, Nicholas J Kepler, Craig S Sander, Christopher A Spence, Raymond T Lee, John C Holst, Stephen C Horne: Forming local interconnects in integrated circuits. Advanced Micro Devices, Foley & Lardner, April 18, 2000: US06051881 (13 worldwide citation)

A method and the resulting device to permit the formation of minimal insulating space between polysilicon gates by forming an insulating layer over the polysilicon gates and protecting selected ones of the gates and the insulating layer with an etch barrier so that the opening for local interconnect ...


7
Craig S Sander, Richard K Klein, Tat C Choi: Reduced area butting contact structure. Advanced Micro Devices, Ashen Golant Martin & Selden, March 27, 1990: US04912540 (9 worldwide citation)

A reduced area butting contact structure (10') is provided, which is especially suited for four-transistor static RAM cells. A structure is formed which includes a doped silicon region and one or more layers of polysilicon and oxide situated thereabove, one of which layers of polysilicon may be a ga ...


8
Stephen C Horne, Richard K Klein, Asim A Selcuk, Nicholas John Kepler, Christopher A Spence, Raymond T Lee, John C Holst: Memory device using a reduced word line voltage during read operations and a method of accessing such a memory device. Advanced Micro Devices, Foley & Lardner, August 18, 1998: US05796651 (9 worldwide citation)

A memory device uses a reduced word line voltage during READ operations. The memory device includes a memory cell and a pass transistor for accessing the cell. The cell includes a storage node coupled to a pull-down transistor having substantially the same conductivity as the pass transistor. A driv ...


9
Nicholas John Kepler, Asim A Selcuk, Richard K Klein, Craig S Sander, John C Holst, Christopher A Spence, Raymond T Lee, Stephen C Horne: Memory cell having increased capacitance via a local interconnect to gate capacitor and a method for making such a cell. Advanced Micro Devices, Foley & Lardner, December 1, 1998: US05844836 (7 worldwide citation)

A static random access memory (SRAM) cell having increased cell capacitance at the storage nodes utilizes a capacitive structure. The capacitive structure includes a dielectric material between polysilicon conductive lines and tungsten local interconnects. The polysilicon plates are each connected t ...


10
Richard K Klein, Darrell M Erb, Steven Avanzino, Robin Cheung, Scott Luning, Bryan Tracy, Subhash Gupta, Ming Ren Lin: Copper pellet for reducing electromigration effects associated with a conductive via in a semiconductor device. Advanced Micro Devices, Foley & Lardner, June 17, 1997: US05639691 (7 worldwide citation)

A multilayer semiconductor structure includes a conductive via. The conductive via includes a pellet of metal having a high resistance to electromigration. The pellet is made from a conformal layer of copper or gold deposited over the via to form a copper or gold reservoir or contact located in the ...



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