1
John Michael Borkenhagen, Richard James Eickemeyer, William Thomas Flynn, Sheldon Bernard Levenstein, Andrew Henry Wottreng: Thread switch control in a multithreaded processor system. International Business Machines Corporation, Karuna Ojanen, May 20, 2003: US06567839 (208 worldwide citation)

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread h ...


2
John Michael Borkenhagen, Richard James Eickemeyer, William Thomas Flynn, Andrew Henry Wottreng: Method and apparatus to force a thread switch in a multithreaded processor. International Business Machines Corporation, Karuna Ojanen, June 13, 2000: US06076157 (177 worldwide citation)

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread h ...


3
John Michael Borkenhagen, Richard James Eickemeyer, William Thomas Flynn, Andrew Henry Wottreng: Method and apparatus for selecting thread switch events in a multithreaded processor. International Business Machines Corporation, Karuna Ojanen, February 24, 2004: US06697935 (147 worldwide citation)

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread h ...


4
Richard James Eickemeyer, Harold F Kossman: Multithreaded processor incorporating a thread latch register for interrupt service new pending threads. International Business Machines Corporation, Min Xu, Merchant Gould Smith Edell Welter & Schmidt, May 9, 2000: US06061710 (118 worldwide citation)

A method of using multithreading resources for improving handling instructions is operated by an improved multithreaded processor which includes a context select logic unit being arranged and configured for receiving and responding an interrupt including: a first controller for setting a pending thr ...


5
Richard James Eickemeyer: Selective flush of shared and other pipeline stages in a multithread processor. International Business Machines Corporation, Karuna Ojanen, February 17, 2004: US06694425 (74 worldwide citation)

In a simultaneous multithread processor, a flush mechanism of a shared pipeline stage is disclosed. In the preferred embodiment, the shared pipeline stage happens to be one or all of the fetch stage, the decode stage, and/or the dispatch stage and the flush mechanism flushes instructions at the disp ...


6
John Michael Borkenhagen, Richard James Eickemeyer, William Thomas Flynn, Steven R Kunkel, Sheldon Bernard Levenstein, Andrew Henry Wottreng: Apparatus and method to guarantee forward progress in execution of threads in a multithreaded processor. International Business Machines Corporation, Karuna Ojanen, Birch Stewart Kolasch & Birch, August 15, 2000: US06105051 (69 worldwide citation)

A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread h ...


7
Richard James Eickemeyer, Ross Evan Johnson, Harold F Kossman, Steven Raymond Kunkel, Timothy John Mullins, James Allen Rose: Method and system for multi-thread switching only when a cache miss occurs at a second or higher level. International Business Machines Corporation, Jack V Musgrove, Andrew J Dillon, Felsman Bradley Vaden Gunter & Dillon, April 11, 2000: US06049867 (55 worldwide citation)

A method and system for enhanced performance multithread operation in a data processing system which includes a processor, a main memory store and at least two levels of cache memory. At least one instruction within an initial thread is executed. Thereafter, the state of the processor at a selected ...


8
James L Denton, Richard James Eickemeyer, Kevin Curtis Griffin, Ross Evan Johnson, Steven Raymond Kunkel, Mikko Herman Lipasti, Sandra Kay Ryan: System and method for increasing cache efficiency through optimized data allocation. International Business Machines Corporation, Terrance A Meador, July 22, 1997: US05651136 (43 worldwide citation)

Logic for decreasing the number of cache lines dedicated to user data. When pools for allocation are selected using a dynamic storage allocation procedure, the size of a data block is compared to the size of the allocated pool. If the comparison results meet a predetermined criterion, the logic alig ...


9
Richard James Eickemeyer, Steven R Kunkel, Hung Q Le: Shared resource queue for simultaneous multithreading processing wherein entries allocated to different threads are capable of being interspersed among each other and a head pointer for one thread is capable of wrapping around its own tail in order to access a free entry. International Business Machines Corporation, Karuna Ojanen, January 17, 2006: US06988186 (30 worldwide citation)

A queue, such as a first-in first-out queue, is incorporated into a processing device, such as a multithreaded pipeline processor. The queue may store the resources of more than one thread in the processing device such that the entries of one thread may be interspersed among the entries of another t ...


10
Richard James Eickemeyer, Ronald Nick Kalla: Effective-to-real address cache managing apparatus and method. International Business Machines Corporation, Birch Stewart Kolasch & Birch, February 1, 2000: US06021481 (22 worldwide citation)

An effective-to-real address translation cache management apparatus and method utilizes an effective-to-real address translation cache segment register latch having a bit corresponding to each of the segment registers. When a segment register is utilized to perform an effective-to-real address trans ...