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Sharad Saxena, Amy J Unruh, Purnendu K Mozumder, Richard G Burch: Process flow design at the module effects level through the use of acceptability regions. Texas Instruments Incorporated, Bret J Petersen, Richard L Donaldson, June 15, 1999: US05912678 (115 worldwide citation)

Methods and processes to reduce the cost and cycle time of designing manufacturing flows are described, particularly for microelectronic integrated circuit processes. One embodiment of the present invention is a method which divides the task of designing process flows into a number of abstraction le ...


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Joseph C Davis, Karthik Vasanth, Sharad Saxena, Purnendu K Mozumder, Suraj Rao, Chenjing L Fernando, Richard G Burch: Method and system for using response-surface methodologies to determine optimal tuning parameters for complex simulators. Texas Instruments Incorporated, Wade James Brady III, Frederick J Telecky Jr, April 30, 2002: US06381564 (53 worldwide citation)

A method and system for providing optimal tuning for complex simulators. The method and system include initially building at least one RSM model having input and output terminals. Then there is provided a simulation-free optimization function by constructing an objective function from the outputs at ...


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Sharad Saxena, Karthik Vasanth, Richard G Burch, Purnendu K Mozumder, Suraj Rao, Joseph C Davis: Design of microelectronic process flows for manufacturability and performance. Texas Instruments Incorporated, Carlton H Hoel, W James Brady, Frederick J Telecky Jr, October 30, 2001: US06311096 (21 worldwide citation)

A statistical design method is provided for minimizing the impact of manufacturing variations on semiconductor manufacturing by statistical design which seeks to reduce the impact of variability on device behavior. The method is based upon a Markov representation of a process flow which captures the ...


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Karthik Vasanth, Sharad Saxena, Richard G Burch, Purnendu K Mozumder, Joseph C Davis, Chenjing L Fernando, Suraj Rao: Integrating dual supply voltages using a single extra mask level. Texas Instruments Incorporated, Jacqueline J Garner, Wade James Brady III, Frederick J Telecky Jr, May 14, 2002: US06388288 (3 worldwide citation)

Integration of dual voltages on a single chip can be accomplished with a minimum of extra masks by optimizing only the MDD implant of the peripheral transistors, while other implants remain the same for both transistor types. This meets lifetime specifications without unnecessary expense.


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Gabriel G Barna, Joseph C Davis, Purnendu K Mozumder, Richard G Burch: Equipment evaluation and design. Texas Instruments Incorporated, Carlton H Hoel, W James Brady, Frederick J Telecky Jr, August 20, 2002: US06438439 (1 worldwide citation)

A semiconductor processing tool evaluation and design method which replaces tool specifications with a requirements region plus associated evaluation functions for iterative feedback tool design.



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