1
Richard E Kessler, Steven M Oberlin, Steven L Scott: Messaging in distributed memory multiprocessing system having shell circuitry for atomic control of message storage queues tail pointer structure in local memory. Cray Research, Schwegman Lundberg Woessner and Kluth P A, November 24, 1998: US05841973 (154 worldwide citation)

A messaging facility in a multiprocessor computer system includes assembly circuitry in a source processing element for assembling a message to be sent from the source processing element to a destination processing element based on information provided from a processor in the source processing eleme ...


2
Richard E Kessler, Steven M Oberlin, Steven L Scott: Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller. Cray Research, Schwegman Lundberg Woessner and Kluth P A, January 26, 1999: US05864738 (130 worldwide citation)

A system and method of transferring information between a peripheral device and an MPP system having an interconnect network and a plurality of processing nodes. Each processing element includes a processor, local memory and a router circuit connected to the interconnect network, the processor and t ...


3
Richard E Kessler, David A Carlson, Muhammad Raghib Hussain, Robert A Sanzone, Khaja E Ahmed, Michael D Varga: Interface for a security coprocessor. Cavium Networks, Blakely Sokoloff Taylor & Zafman, September 7, 2004: US06789147 (82 worldwide citation)

A method and apparatus for processing security operations are described. In one embodiment, a processor includes a number of execution units to process a number of requests for security operations. The number of execution units are to output the results of the number of requests to a number of outpu ...


4
Richard E Kessler, Steven M Oberlin, Gregory M Thorson: Barrier and eureka synchronization architecture for multiprocessors. Cray Research, Schwegman Lundberg Woessner & Kluth P A, February 24, 1998: US05721921 (79 worldwide citation)

Method and apparatus for facilitating barrier and eureka synchronization in a massively parallel processing system. The present barrier/eureka mechanism provides a partitionable, low-latency, immediately reusable, robust mechanism which can operate on a physical data-communications network and can b ...


5
Mark S Birrittella, Richard E Kessler, Steven M Oberlin, Randal S Passint, Greg Thorson: System for allocating messages between virtual channels to avoid deadlock and to optimize the amount of message traffic on each type of virtual channel. Cray Research, Lundberg Woessner & Kluth P A Schwegman, December 10, 1996: US05583990 (72 worldwide citation)

A multidimensional interconnection and routing apparatus for a parallel processing computer connects together processing elements in a three-dimensional structure. The interconnection and routing apparatus includes a plurality of processing element nodes. A communication connects at least one of the ...


6
David Arthur James Webb Jr, Richard E Kessler, Steve Lang: Special encoding of known bad data. Hewlett Packard Development Company, August 29, 2006: US07100096 (69 worldwide citation)

A multi-processor system in which each processor receives a message from another processor in the system. The message may contain corrupted data that was corrupted during transmission from the preceding processor. Upon receiving the message, the processor detects that a portion of the message contai ...


7
Richard E Kessler, Samuel H Duncan, David W Hartwell, David A J Webb Jr, Steve Lang: Scalable efficient I/O port protocol. Hewlett Packard Development Company, May 18, 2004: US06738836 (69 worldwide citation)

A system that supports a high performance, scalable, and efficient I/O port protocol to connect to I/O devices is disclosed. A distributed multiprocessing computer system contains a number of processors each coupled to an I/O bridge ASIC implementing the I/O port protocol. One or more I/O devices ar ...


8
Richard E Kessler, Steven M Oberlin, Steven L Scott, Subbarao Palacharla: Stream buffers for high-performance computer memory system. Cray Research, Schwegman Lundberg Woessner & Kluth P A, June 2, 1998: US05761706 (64 worldwide citation)

Method and apparatus for a filtered stream buffer coupled to a memory and a processor, and operating to prefetch data from the memory. The filtered stream buffer includes a cache block storage area and a filter controller. The filter controller determines whether a pattern of references has a predet ...


9
David A J Webb Jr, Richard E Kessler, Steve Lang, Aaron T Spink: Broadcast invalidate scheme. Hewlett Packard Development Company, June 15, 2004: US06751721 (52 worldwide citation)

A directory-based multiprocessor cache control scheme for distributing invalidate messages to change the state of shared data in a computer system. The plurality of processors are grouped into a plurality of clusters. A directory controller tracks copies of shared data sent to processors in the clus ...


10
Gregg A Bouchard, David A Carlson, Richard E Kessler: Selective replication of data structures. Cavium Networks, Hamilton Brook Smith & Reynolds P C, July 7, 2009: US07558925 (51 worldwide citation)

Methods and apparatus are provided for selectively replicating a data structure in a low-latency memory. The memory includes multiple individual memory banks configured to store replicated copies of the same data structure. Upon receiving a request to access the stored data structure, a low-latency ...