1
Ricardo H Bruce, Rolando H Bruce, Earl T Cohen, Allan J Christie: Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage. BIT Microsystems, Stuart T Auvinen, December 7, 1999: US06000006 (555 worldwide citation)

A flash-memory system provides solid-state mass storage as a replacement to a hard disk. A unified re-map table in a RAM is used to arbitrarily re-map all logical addresses from a host system to physical addresses of flash-memory devices. Each entry in the unified re-map table contains a physical bl ...


2
Ricardo H Bruce, Rolando H Bruce, Earl T Cohen: Expandable flash-memory mass-storage using shared buddy lines and intermediate flash-bus between device-specific buffers and flash-intelligent DMA controllers. Bit Microsystems, Stuart T Auvinen, October 13, 1998: US05822251 (129 worldwide citation)

A flash-memory system is expandable. Rather than directly connecting individual flash-memory chips to a controller, flash buffer chips are used. Each flash buffer chip can connect to four banks of flash-memory chips. Chip enables for individual chips in a bank are generated from an address sent to t ...


3
Ricardo H Bruce, Rolando H Bruce, Earl T Cohen: Transparent management at host interface of flash-memory overhead-bytes using flash-specific DMA having programmable processor-interrupt of high-level operations. Bit Microsystems, Stuart T Auvinen, September 21, 1999: US05956743 (128 worldwide citation)

A flash-memory system adds system-overhead bytes to each page of data stored in flash memory chips. The overhead bytes store system information such as address pointers for bad-block replacement and write counters used for wear-leveling. The overhead bytes also contain an error-correction (ECC) code ...


4
Shun Hang Luk, Rey H Bruce, Ricardo H Bruce, Dave L Bultman: Network storage device having solid-state non-volatile memory. Shabneez Kotadia, Stephen Uriarte, December 27, 2005: US06981070 (100 worldwide citation)

A network storage device. In one embodiment, the network storage device of the present invention uses solid-state non-volatile memory (e.g., flash-memory) as a storage medium, and has at least one interface configured for coupling to a computer network. The network storage device of the present inve ...


5
Ricardo H Bruce, Rolando H Bruce: Method and apparatus for data recovery. BiTMicro Networks, Shabneez Kotadia, Stephen Uriarte, Mikio Ishimaru, November 29, 2005: US06970890 (61 worldwide citation)

A method for recovering data in a storage device is provided in which information related to a first data structure is defined with a plurality of copies of a second data structure and the information related to the first data structure is rebuilt using the plurality of copies of the second data str ...


6
Roland F Portman, Ricardo H Bruce: Method and system for controlling data in a computer system in the event of a power failure. Bit Microsystems, Sawyer Law Group, December 17, 2002: US06496939 (48 worldwide citation)

A method and system for controlling data in a computer system when the computer system loses power is disclosed. The method and system comprises activating a plurality of super capacitors to supply power to the computing engine based upon power being removed from the computer system and reconfigurin ...


7
Ricardo H Bruce, Rolando H Bruce: Parallel erase operations in memory systems. BiTMICRO Networks, Mikio Ishimaru, Stephen R Uriarte, March 4, 2003: US06529416 (45 worldwide citation)

An apparatus for and method of memory operation having a memory, a cache containing a plurality of entries with a plurality of the entries to be written to memory, a detector for detecting in the cache the plurality of entries to be written to memory, and a processor for erasing a first portion of t ...


8
Ricardo H Bruce, Elsbeth Lauren T Villapana, Joel A Baylon: Multilevel memory bus system for solid-state mass storage. BiTMICRO Networks, Stephen Uriarte, May 21, 2013: US08447908 (34 worldwide citation)

The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA contro ...


9
Rey H Bruce, Ricardo H Bruce, Elsbeth Lauren Tagayo VillapaƱa: Reduced latency memory read transactions in storage devices. BiTMICRO Networks, Stephen Uriarte, February 17, 2015: US08959307 (32 worldwide citation)

A solution for performing reduced latency memory read transactions is disclosed. In one example, a storage apparatus has a memory array that includes: a flash device having a data register, a memory interface coupled to the memory array and a buffer set that includes at least one buffer suitable for ...


10
Ricardo H Bruce, Marlon B Verdan, Margaret Anne N Somera, Rowenah Michelle D Jago on, Maria Eliza B De Belen, Ron Kelvin B Palacol: Multi-profile memory controller for computing devices. BiTMICRO Networks, Stephen Uriarte, September 15, 2015: US09135190 (30 worldwide citation)

The present invention pertains to a multi-profile memory controller and devices that use multi-profile memory controllers. More particularly, the present invention pertains to a multi-profile memory controller and related methods and systems that can operate with memory locations, memory devices, or ...