1
Rebecca L Stamm: Method and apparatus for ordering read and write operations using conflict bits in a write queue. Digital Equipment Corporation, James F Thompson, Ronald C Hudgens, July 11, 1995: US05432918 (132 worldwide citation)

A method and apparatus for controlling memory access operations of a pipelined processor using a "write queue" are described. The write queue temporarily stores addresses of writes not yet made in memory. Each write queue entry includes a write-read conflict bit. When an entry is first put into the ...


2
Rebecca L Stamm, Ruth I Bahar, Raymond L Strouble, Nicholas D Wade, John H Edmondson: Ensuring write ordering under writeback cache error conditions. Digital Equipment Corporation, Arnold White & Durkee, September 13, 1994: US05347648 (118 worldwide citation)

Writeback transactions from a processor and cache are fed to a main memory through a writeback queue, and non-writeback transactions from the processor and cache are fed to the main memory through a non-writeback queue. When a cache error is detected, an error transition mode (ETM) is entered that p ...


3
Rebecca L Stamm, Nicholas D Wade: Processor and method for preventing access to a locked memory block by recording a lock in a content addressable memory with outstanding cache fills. Digital Equipment Corporation, Denis G Maloney, Arthur W Fisher, April 4, 1995: US05404482 (116 worldwide citation)

A processor and method for preventing access to a locked memory block in a multiprocessor computer system. The processor has a cache memory and records a memory lock in a content-addressable memory separate from the cache memory. Preferably, outstanding cache fills are recorded in the same content a ...


4
Rebecca L Stamm, John Edmondson, David Archer, Samyojita Nadkarni, Raymond Strouble: Processor system with writeback cache using writeback and non writeback transactions stored in separate queues. Digital Equipment Corporation, Richard J Paciulan, Denis G Maloney, May 31, 1994: US05317720 (114 worldwide citation)

A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. A writeback cache is used (instead of writethrough) in a hierarchical cache arrangement, and writeback is allowed to proceed even though other accesses are suppressed due to queues being full ...


5
Joel S Emer, Rebecca L Stamm, Bruce E Edwards, Matthew H Reilly, Craig B Zilles, Tryggve Fossum, Christopher F Joerg, James E Hicks Jr: Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit. Compaq Information Technologies Group, Hamilton Brook Smith & Reynolds P C, December 10, 2002: US06493741 (112 worldwide citation)

Execution of a program's instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as ...


6
Rebecca L Stamm, R Iris Bahar, Michael Callander, Linda Chao, Derrick R Meyer, Douglas Sanders, Richard L Sites, Raymond Strouble, Nicholas Wade: Error transition mode for multi-processor system. Digital Equipment Corporation, Arnold White & Durkee, October 13, 1992: US05155843 (106 worldwide citation)

A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queueing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth ...


7
Richard T Witek, Douglas D Williams, Timothy J Stanley, David M Fenwick, Douglas J Burns, Rebecca L Stamm, Richard Heye: Pipeline having an integral cache which processes cache misses and loads data in parallel. Digital Equipment Corporation, Kenyon & Kenyon, September 15, 1992: US05148536 (96 worldwide citation)

A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained ind ...


8
W Hugh Durdan, Rebecca L Stamm, G Michael Uhler: Method and apparatus for filtering invalidate requests. Digital Equipment Corporation, Arnold White & Durkee, October 15, 1991: US05058006 (78 worldwide citation)

An apparatus which filters the number of invalidates to be propagated onto a private processor bus is provided. This is desirable so that the processor bus is not overloaded with invalidate requests. The present invention describes a method of filtering the number of invalidates to be propagated to ...


9
Rebecca L Stamm, Ruth I Bahar, Nicholas D Wade: Processor and method for delaying the processing of cache coherency transactions during outstanding cache fills. Digital Equipment Corporation, Denis G Maloney, Arthur W Fisher, April 4, 1995: US05404483 (71 worldwide citation)

A processor and method for delaying the processing of cache coherency transactions during outstanding cache fills in a multi-processor system using a shared memory. A first processor fetches data having a specified address by addressing a cache memory, and when the specified address is not in the ca ...


10
Rebecca L Stamm, G Michael Uhler: Conversion of internal processor register commands to I/O space addresses. Digital Equipment Corporation, Arnold White & Durkee, January 2, 1996: US05481689 (69 worldwide citation)

A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queuing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth i ...