1
Rebecca L Stamm, John Edmondson, David Archer, Samyojita Nadkarni, Raymond Strouble: Processor system with writeback cache using writeback and non writeback transactions stored in separate queues. Digital Equipment Corporation, Richard J Paciulan, Denis G Maloney, May 31, 1994: US05317720 (114 worldwide citation)

A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. A writeback cache is used (instead of writethrough) in a hierarchical cache arrangement, and writeback is allowed to proceed even though other accesses are suppressed due to queues being full ...


2
Rebecca L Stamm, R Iris Bahar, Michael Callander, Linda Chao, Derrick R Meyer, Douglas Sanders, Richard L Sites, Raymond Strouble, Nicholas Wade: Error transition mode for multi-processor system. Digital Equipment Corporation, Arnold White & Durkee, October 13, 1992: US05155843 (106 worldwide citation)

A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queueing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth ...


3
Mary C Stock, Raymond Strouble, Ernest P Walker: Test system for integrated circuits using a single memory for both the parallel and scan modes of testing. April 11, 2000: US06049901 (11 worldwide citation)

A semiconductor test system has a scan test mode and a parallel test mode. A single memory using substantially all of its storage space stores a) parallel test vectors for use during the parallel test mode, and b) parallel test vectors and scan test vectors for use during the scan test mode. A switc ...