1
Ravi L Sahita, David M Durham, Prashant Dewan, Manohar R Castelino: Method and apparatus for transparently instrumenting an application program. Intel Corporation, Grossman Tucker Perreault & Pfleger PLLC, July 2, 2013: US08479295 (12 worldwide citation)

Generally, this disclosure describes systems and methods for transparently instrumenting a computer process. The systems and methods are configured to allow instrumenting executable code while permitting legacy memory scanning tools to monitor corresponding uninstrumented executable code stored in m ...


2
Ravi L Sahita, Uday R Savagaonkar, Vedvyas Shanbhogue, Ernest F Brickell: Software copy protection via protected execution of applications. Intel Corporation, Caven & Aghevli, June 18, 2013: US08468356 (7 worldwide citation)

Methods and apparatus to provide a tamper-resistant environment for software are described. In some embodiments, procedures for verifying whether a software container is utilizing protected memory and is associated with a specific platform are described. Other embodiments are also described.


3
Ravi L Sahita, Xiaoning Li, Manohar R Castelino: Secure handling of interrupted events utilizing a virtual interrupt definition table. Intel Corporation, Schwabe Williamson & Wyatt P C, November 5, 2013: US08578080 (7 worldwide citation)

Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views between programs while still protecting critical regions of the memory from attacks of malwares. Other embodiments may be disclosed and claime ...


4
Ravi L Sahita: Statistics collection framework for a network processor. Intel Corporation, Marger Johnson & McCollom P C, June 16, 2009: US07548944 (6 worldwide citation)

Methods and devices for wire-speed packet statistics collection in a network processor are disclosed. A control-plane process maintains a dynamic packet rule set, each rule specifying a packet offset, a data pattern to be found at that offset, and an action to be taken if that data pattern is found. ...


5
Ravi L Sahita, David M Durham, Steve Orrin, Yasser Rasheed, Prasanna G Mulgaonkar, Paul S Schmitz, Hormuzd M Khosravi: Computer system and method with anti-malware. Intel Corporation, Erik R Nordstrom, January 21, 2014: US08635705 (4 worldwide citation)

In some embodiments, approaches may provide an out-of-band (OOB) agent to protect a platform. The OOB agent may be able to use non-TRS methods to measure and protect an in-band security agent. In some embodiments, a manageability engine can provide out of band connectivity to the in-band and out-of- ...


6
David M Durham, Ravi L Sahita, Dylan C Larson, Rajendra S Yavatkar: Page coloring to associate memory pages with programs. Intel Corporation, Thomas R Lane, July 12, 2016: US09390031 (3 worldwide citation)

Apparatuses and methods for page coloring to associate memory pages with programs are disclosed. In one embodiment, an apparatus includes a paging unit and an interface to access a memory. The paging unit includes translation logic and comparison logic. The translation logic is to translate a first ...


7
Ravi L Sahita, Xiaoning Li, Manohar R Castelino: Low overhead paged memory runtime protection. Intel Corporation, Alpine Technology Law Group, February 23, 2016: US09268707 (2 worldwide citation)

Methods and apparatus relating to low overhead paged memory runtime protection are described. In an embodiment, permission information for guest physical mapping are received prior to utilization of paged memory by an Operating System (OS) based on the guest physical mapping. The permission informat ...


8
Ravi L Sahita, David M Durham, Gilbert Neiger, Andrew V Anderson, Scott D Rodgers: Low latency virtual machine page table management. Intel Corporation, Thomas R Lane, August 2, 2016: US09405570 (2 worldwide citation)

Various embodiments of this disclosure may describe method, apparatus and system for reducing system latency caused by switching memory page permission views between programs while still protecting critical regions of the memory from attacks of malwares. Other embodiments may be disclosed and claime ...


9
Ravi L Sahita, Vedvyas Shanbhogue: Providing supervisor control of control transfer execution profiling. Intel Corporation, Trop Pruner & Hu P C, April 18, 2017: US09626508 (1 worldwide citation)

In one embodiment, an apparatus includes a control transfer termination (CTT) state machine configured to raise a fault when an indirect control transfer instruction of a process is not terminated by a CTT instruction. A virtual machine monitor (VMM) is configured to selectively enable the CTT state ...


10
Ravi L Sahita, Gilbert Neiger, David M Durham, Vedvyas Shanbhogue, Michael Lemay, Ido Ouziel, Stanislav Shwartsman, Barry Huntley, Andrew V Anderson: Validating virtual address translation by virtual machine monitor utilizing address validation structure to validate tentative guest physical address and aborting based on flag in extended page table requiring an expected guest physical address in the address validation structure. Intel Corporation, Lowenstein Sandler, October 17, 2017: US09792222 (1 worldwide citation)

Systems and methods for validating virtual address translation. An example processing system comprises: a processing core to execute a first application associated with a first privilege level and a second application associated with a second privilege level, wherein a first set of privileges associ ...