1
Guy Lynn Guthrie, Ravi Kumar Arimilli, John Steven Dodson, Derek Edward Williams: Multi-level multiprocessor speculation mechanism. International Business Machines Corporation, Casimer K Salys, Bracewell & Patterson L, June 8, 2004: US06748518 (86 worldwide citation)

Disclosed is a processor, which reduces issuing of unnecessary barrier operations during instruction processing. The processor comprises an instruction sequencing unit and a load store unit (LSU) that issues a group of memory access requests that precede a barrier instruction in an instruction seque ...


2
Ravi Kumar Arimilli, John Michael Kaiser: Queued arbitration mechanism for data processing system. International Business Machines Corporation, Kelly K Winstead Sechrest & Minick P C Kordzik, Anthony V S England, February 22, 2000: US06029217 (75 worldwide citation)

A queued arbitration mechanism transfers all queued processor bus requests to a centralized system controller/arbiter in a descriptive and pipelined manner. Transferring these descriptive and pipelined bus requests to the system controller allows the system controller to optimize the system bus util ...


3
Ravi Kumar Arimilli, Leo James Clark, James Stephen Fields Jr, Guy Lynn Guthrie: Multiprocessor system in which a cache serving as a highest point of coherency is indicated by a snoop response. International Business Machines Corporation, Casimer K Salys, Bracewell & Patterson L, June 11, 2002: US06405289 (73 worldwide citation)

A method of maintaining cache coherency, by designating one cache that owns a line as a highest point of coherency (HPC) for a particular memory block, and sending a snoop response from the cache indicating that it is currently the HPC for the memory block and can service a request. The designation ...


4
Ravi Kumar Arimilli, Lakshminarayana Baba Arimilli, Leo James Clark, John Steven Dodson, Guy Lynn Guthrie, James Stephen Fields Jr: Optimized cache allocation algorithm for multiple speculative requests. International Business Machines Corporation, Casimer K Salys, Bracewell & Patterson L, May 21, 2002: US06393528 (60 worldwide citation)

A method of operating a computer system is disclosed in which an instruction having an explicit prefetch request is issued directly from an instruction sequence unit to a prefetch unit of a processing unit. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardwar ...


5
Ravi Kumar Arimilli, James Stephen Fields Jr, Guy Lynn Guthrie, Jody Bern Joyner, Jerry Don Lewis: Multiprocessor system bus protocol with group addresses, responses, and priorities. International Business Machines Corporation, Casimer K Salys, Bracewell & Patterson L, July 8, 2003: US06591321 (60 worldwide citation)

A multiprocessor system bus protocol system and method for processing and handling a processor request within a multiprocessor system having a number of bus accessible memory devices that are snooping on. at least one bus line. Snoop response groups which are groups of different types of snoop respo ...


6
Ravi Kumar Arimilli, James Stephen Fields Jr, Guy Lynn Guthrie, Jody Bern Joyner, Jerry Don Lewis: Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response. International Business Machines Corporation, Casimer K Salys, Dillon & Yudell, January 25, 2005: US06848003 (48 worldwide citation)

A data processing system includes a plurality of nodes, which each contain at least one agent and each have an associated node identifier, and memory distributed among the plurality of nodes. The data processing system further includes an interconnect containing a segmented data channel, where each ...


7
Ravi Kumar Arimilli, Lakshminarayana Baba Arimilli, James Stephen Fields Jr: Method of cache management to dynamically update information-type dependent cache policies. International Business Machines Corporation, Casimer K Salys, Bracewell & Patterson L, August 13, 2002: US06434669 (48 worldwide citation)

A set associative cache includes a cache controller, a directory, and an array including at least one congruence class containing a plurality of sets. The plurality of sets are partitioned into multiple groups according to which of a plurality of information types each set can store. The sets are pa ...


8
Ravi Kumar Arimilli, Kevin F Reick: Method and apparatus for servicing a processing system through a test port. International Business Machines Corporation, Casimer K Slays, Bracewell & Patterson L, September 30, 2003: US06629268 (42 worldwide citation)

A method and apparatus for servicing a processing system through a test port allow initialization and fault recovery capability including the ability to coherently access cache memory while the processing system is operating. A JTAG standard interface is used to access registers in a main processing ...


9
Ravi Kumar Arimilli, John Steven Dodson, Jerry Don Lewis: High performance cache directory addressing scheme for variable cache sizes utilizing associativity. International Business Machines Corporation, Volel Emile, Felsman Bradley Vaden Gunter & Dillon, February 20, 2001: US06192458 (41 worldwide citation)

To avoid multiplexing within the critical address paths, the same address field is employed as a index to the cache directory and cache memory regardless of the cache memory size. An increase in cache memory size is supported by increasing associativity within the cache directory and memory, for exa ...


10
Lakshminarayana Baba Arimilli, Ravi Kumar Arimilli, James Stephen Fields Jr: Method and system for bypassing cache levels when casting out from an upper level cache. International Business Machines Corporation, Casimer K Salys, Bracewell & Patterson L, March 12, 2002: US06356980 (41 worldwide citation)

A method and system for bypassing cache levels when storing data castout from an upper level cache provides a memory hierarchy that can selectively skip one more more intermediate levels when writing castout entries from a higher level cache based on a number of detected conditions. The intermediate ...