1
Tyler A Lowrey, Randal W Chance, David A Cathey: Method for reducing, by a factor or 2.sup.-N, the minimum masking pitch of a photolithographic process. Micron Technology, Angus C Fox III, July 12, 1994: US05328810 (538 worldwide citation)

The process starts with a primary mask, which may be characterized as a pattern of parallel, photoresist strips having substantially vertical edges, each having a minimum feature width F, and being separated from neighboring strips by a minimum space width which is also approximately equal to F. Fro ...


2
Tyler A Lowrey, Randal W Chance, D Mark Durcan, Ruojia Lee, Charles H Dennison, Yauh Ching Liu, Pierre C Fazan, Fernando Gonzalez, Gordon A Haller: Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography. Micron Technology, Angus C Fox III, Stanley N Protigal, May 7, 1991: US05013680 (288 worldwide citation)

A process for creating a DRAM array having feature widths that transcend the resolution limit of the employed photolithographic process using only five photomasking steps. The process involves the following steps: creation of a half-pitch hard-material mask that is used to etch a series of equidista ...


3
Randal W Chance: Method of manufacturing edge connected semiconductor die. Micron Technology, Stanley N Protigal, June 30, 1992: US05126286 (151 worldwide citation)

Die bond locations on a semiconductor die are formed as vertical inserts along the edge of the die. The vertical inserts are isolated from substrate and are exposed by a wafer saw process, in which dice are singulated from a wafer. The configuration offers the advantages of a more efficient layout, ...


4
Randal W Chance, Gordon A Haller, Sanh D Tang, Steven D Cummings: Methods of forming semiconductor constructions. Micron Technology, Wells St John P S, October 17, 2006: US07122425 (76 worldwide citation)

The invention includes semiconductor constructions containing vertically-extending pillars, and methods for forming such constructions. The vertically-extending pillars can be incorporated into transistor devices, and can contain vertically-extending channel regions of the transistor devices. The tr ...


5
Tyler A Lowrey, Randal W Chance: Static discharge circuit having low breakdown voltage bipolar clamp. Micron Technology, Schwegman Lundberg Woessner & Kluth P A, December 3, 1996: US05581104 (51 worldwide citation)

A bipolar transistor and a bipolar diode are provided at an input pad on an integrated circuit, in order to shunt potential surges caused by electrostatic discharge (ESD). The approach makes use of a bipolar and a diode clamp with an optimized reverse biased breakdown from collector to base to shunt ...


6
Randal W Chance, Eugene H Cloud: Semiconductor package utilizing edge connected semiconductor dice. Micron Technology, Stanley N Protigal, September 8, 1992: US05146308 (44 worldwide citation)

Die bond locations on a semiconductor die are formed as vertical inserts along the edge of the die. The vertical inserts are isolated from substrate and are exposed by a wafer saw process, in which dice are singulated from a wafer. The configuration offers the advantages of a more efficient layout, ...


7
Tyler A Lowrey, Randal W Chance: Phase shifting reticle fabrication using ion implantation. Micron Technology, Angus C Fox III, May 4, 1993: US05208125 (44 worldwide citation)

A method of fabricating a phase shifting reticle that can be used as a mask in photolithographic processes such as semiconductor wafer patterning. A transparent quartz substrate is subjected to high voltage ion bombardment to produce patterns of ion implant areas on the substrate. By carefully selec ...


8
Tyler A Lowrey, Randal W Chance, D Mark Durcan, Pierre C Fazan, Fernando Gonzalez, Gordon A Haller: Process for fabricating, on the edge of a silicon mesa, a MOSFET which has a spacer-shaped gate and a right-angled channel path. Micron Technology, Angus C Fox III, January 5, 1993: US05177027 (42 worldwide citation)

A process for fabricating, on the more or less vertical edge of a silicon mesa, a MOS field-effect transistor which has a spacer-shaped gate and a right-angled channel path. The process involves the following steps: creating a raised region (the mesa) on a planar silicon substrate; creation of a gat ...


9
Tyler A Lowrey, Randal W Chance, Ward D Parkinson: Split-polysilicon CMOS process incorporating unmasked punchthrough and source/drain implants. Micron Technology, Angus C Fox III, Stanley N Protigal, July 16, 1991: US05032530 (37 worldwide citation)

An improved CMOS fabrication process which uses separate masking steps to pattern N-channel and P-channel transistor gates from a single layer of conductively-doped polycrystalline silicon (poly). The object of the improved process is to reduce the cost and improve the reliability and manufacturabil ...


10
Gurtej S Sandhu, Randal W Chance, William T Rericha: Method to align mask patterns. Micron Technology, Knobbe Martens Olson & Bear, November 25, 2008: US07455956 (31 worldwide citation)

Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pitch multiplication and the wider ma ...