1
Kluth George Jonathan, Clark Phelps Robert B, Jeon Joong S, Zhong Huicai, Halliyal Arvind, Ramsbey Mark T, Ogle Robert Bertram Jr, Chang Kuo Tung, Li Wenmei: Memory cell structure having nitride layer with reduced charge loss and method for fabricating same. Advanced Micro Devices, Kluth George Jonathan, Clark Phelps Robert B, Jeon Joong S, Zhong Huicai, Halliyal Arvind, Ramsbey Mark T, Ogle Robert Bertram Jr, Chang Kuo Tung, Li Wenmei, sCOLLOPY Daniel R, March 24, 2005: WO/2005/027210 (2 worldwide citation)

According to one embodiment, a memory cell structure comprises a semiconductor substrate (210), a first silicon oxide layer (215) situated over the semiconductor substrate, a charge storing layer (220) situated over the first silicon oxide layer, a second silicon oxide layer (225) situated over the ...


2
Ngo Minh Van, Ramsbey Mark T, Kamal Tazrien, Gao Pei Yuan: Pecvd silicon-rich oxide layer for reduced uv charging in an eeprom. Advanced Micro Devices, Ngo Minh Van, Ramsbey Mark T, Kamal Tazrien, Gao Pei Yuan, sCOLLOPY Daniel R, February 3, 2005: WO/2005/010984 (1 worldwide citation)

A Si-rich silicon oxide layer (500) having reduced UV transmission is deposited by PECVD, on an interlayer dielectric (300) , prior to metallization, thereby reducing Vt. Embodiments include depositing a UV opaque Si-rich silicon oxide layer (500) having a refractive index (R.I.) of 1.7 to 2.0. The ...


3
Ramsbey Mark T, Kamal Tazrien, Yang Jean Y, Lingunis Emmanuil, Shiraiwa Hidehiko, Sun Yu: Memory manufacturing process with bitline isolation. Fasl, January 5, 2005: EP1493185-A1 (1 worldwide citation)

A method of manufacturing an integrated circuit is provided with a semiconductor substrate having a core region and a periphery region. A charge-trapping dielectric layer is deposited in the core region, and a gate dielectric layer is deposited in the periphery region. Bitlines are formed in the sem ...


4
Ramsbey Mark T, Kamal Tazrien, Yang Jean Y, Lingunis Emmanuil, Shiraiwa Hidehiko: Memory manufacturing process with bitline isolation. Fasl, January 21, 2007: TWI271822 (1 worldwide citation)

A method of manufacturing an integrated circuit is provided with a semiconductor substrate (506) having a core region (502) and a periphery region (504). A charge-trapping dielectric layer (510) is deposited in the core region (502), and a gate dielectric layer (522) is deposited in the periphery re ...


5
Kluth George Jonathan, Clark Phelps Robert B, Jeon Joong S, Halliyal Arvind, Ramsbey Mark T, Ogle Robert Bertram Jr, Chang Kuo Tung, Li Wenmei, Zhong Huicai: Memory cell structure having nitride layer with reduced charge loss and method for fabricating same. Advanced Micro Devices, May 17, 2006: GB2420226-A

According to one embodiment, a memory cell structure comprises a semiconductor substrate (210), a first silicon oxide layer (215) situated over the semiconductor substrate, a charge storing layer (220) situated over the first silicon oxide layer, a second silicon oxide layer (225) situated over the ...


6
Ngo Minh Van, Kamal Tazrien, Ramsbey Mark T, Halliyal Arvind, Park Jaeyong, Cheng Ning, Erhardt Jeff P, Shields Jeffrey A, Ferguson Clarence, Hui Angela T, Huertas Robert A, Gottipati Tyagamohan: Uv-blocking layer for reducing uv-induced charging of sonos dual-bit flash memory devices in beol processing. Advanced Micro Devices, October 26, 2005: GB2413438-A

A method of protecting a SONOS flash memory cell (24) from UV-induced charging, including fabricating a SONOS flash memory cell (24) in a semiconductor device (10, 50); and depositing over the SONOS flash memory cell (24) at least one UV-protective layer (38, 46, 48 or 52), the UV-protective layer i ...


7
Kamal Tazrien, Ngo Minh Van, Ramsbey Mark T, Shields Jeffrey A, Yang Jean Y, Lingunis Emmanuil, Shiraiwa Hidehiko: Memory wordline hard mask extension. Spansion, June 29, 2005: GB2409573-A

A manufacturing method is provided for an integrated circuit memory with closely spaced wordlines (525) (526) formed by using the hard mask extensions (524). A charge-trapping dielectric material (504) is deposited over a semiconductor substrate (501) and first and second bitlines (512) are formed t ...


8
Yang Jean Y, Ramsbey Mark T, Shiraiwa Hidehiko, Wu Yider, Lingunis Emmanuil, Kamal Tazrien: Hard mask process for memory device without bitline shorts. Spansion, May 11, 2005: GB2407913-A

A manufacturing method for a MirrorBit Flash memory includes providing a semiconductor substrate [102] [602] and depositing a charge trapping dielectric layer [504] [606]. First and second bitlines [512] [608] are implanted and a wordline layer [515] is deposited [610]. A hard mask layer [516] is de ...


9
Kamal Tazrien, Ramsbey Mark T, Shiraiwa Hidehiko, Cheung Fred Tk: Charge-trapping memory arrays. Spansion, December 14, 2005: GB2415091-A

The present invention relates to a memory array (100) comprising a substrate (222) and a plurality of bitlines (224) having contacts (240) and a plurality of wordlines (201, 202) intersecting the bitlines (224). A protective spacer (234) is used to separate the bitline contacts (240) from the wordli ...


10
Ramsbey Mark T, Randolph Mark W: Memory device having trapezoidal bitlines and method of fabricating same. Spansion, October 24, 2007: GB2437447-A

A memory device (100) and a method of fabrication are provided. The memory device (100) includes a semiconductor substrate (110) and a charge trapping dielectric stack (116, 118, 120) disposed over the semiconductor substrate (110). A gate electrode (122) is disposed over the charge trapping dielect ...