1
Ramesh Panwar, Joseph I Chamdani: Method of executing coded instructions in a multiprocessor having shared execution resources including active, nap, and sleep states in accordance with cache miss latency. Sun Microsystems, William J Kubida, Stuart T Hogan & Hartson Langley, March 7, 2000: US06035374 (109 worldwide citation)

A method of executing coded instructions in a dynamically configurable multiprocessor having shared execution resources including steps of placing a first processor in an active state upon booting of the multiprocessor. In response to a processor create command, a second processor is placed in an ac ...


2
Fred Gruner, David Hass, Ramesh Panwar, Nazar Zaidi: Sharing a second tier cache memory in a multi-processor. Juniper Networks, Shumaker & Sieffert PA, April 12, 2005: US06880049 (107 worldwide citation)

A set of cache memory includes a set of first tier cache memory and a second tier cache memory. In the set of first tier cache memory each first tier cache memory is coupled to a compute engine in a set of compute engines. The second tier cache memory is coupled to each first tier cache memory in th ...


3
Mark Bryers, Elango Ganesan, Frederick Gruner, David Hass, Robert Hathaway, Ramesh Panwar, Ricardo Ramirez, Abbas Rashid, Mark Vilas, Nazar Zaidi, Yen Lee, Chau Anh Ngoc Nguyen, John Phillips, Yuhong Andy Zhou, Gregory G Spurrier, Sankar Ramanoorthi, Michael Freed: Content service aggregation system. Juniper Networks, Shumaker & Sieffert P A, December 4, 2007: US07305492 (77 worldwide citation)

A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Proto ...


4
Ramesh Panwar, Ricky C Hetherington: Apparatus for dynamically reconfiguring a processor. Sun Microsystems, Philip J McKay, Gunnison McKay & Hodgson L, May 29, 2001: US06240502 (72 worldwide citation)

A method and apparatus for dynamically reconfiguring a processor involves placing the processor in a first configuration having a first number (m) of strands while the coded instructions comprise instructions from a number (m) threads. The instructions in each of the m threads are executed on one of ...


5
Ramesh Panwar, Arjun Prabhu: Computer product for precise architectural update in an out-of-order processor. Sun Microsystems, William J Kubida, Stuart T Holland & Hart Langley, November 17, 1998: US05838988 (65 worldwide citation)

A processor including at least one execution unit generating out-of-order results and out-of-order condition codes. Precise architectural state of the processor is maintained by providing a results buffer having a number of slots and providing a condition code buffer having the same number of slots ...


6
Mark Bryers, Elango Ganesan, Frederick Gruner, David Hass, Robert Hathaway, Ramesh Panwar, Ricardo Ramirez, Abbas Rashid, Mark Vilas, Nazar Zaidi, Yen Lee, Chau Ahn Ngoc Nguyen, John Phillips, Yuhong Andy Zhou, Gregory G Spurrier, Sankar Ramanoorthi, Michael Freed: Content service aggregation system. Juniper Networks, Shumaker & Sieffert P A, July 27, 2010: US07765328 (63 worldwide citation)

A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Proto ...


7
Sanjay Patel, Rajasekhar Cherabuddi, Ramesh Panwar, Adam R Talcott: Cache memory array which stores two-way set associative data. Sun Microsystems, Jones & Volentine L, December 29, 1998: US05854761 (45 worldwide citation)

A cache memory array stores two-way set associative data. An odd set data bank stores odd number sets of the two-way set associative data, where the two ways of each odd number set are aligned horizontally within the odd set data bank. An even set data bank stores even number sets of the two-way set ...


8
Elango Ganesan, Ramesh Panwar, Yen Lee, Chau Anh Ngoc Nguyen, John Phillips, Yuhong Andy Zhou, Gregory G Spurrier, Sankar Ramanoorthi, Michael Freed, Mark Bryers, Nazar Zaidi: Content service aggregation device for a data center. Juniper Networks, Shumaker & Sieffert P A, April 22, 2008: US07363353 (39 worldwide citation)

An architecture for controlling a multiprocessing system to provide at least one network service to subscriber data packets transmitted in the system using a plurality of compute elements, comprising a management compute element including service set-up information for at least one service and at le ...


9
Ramesh Panwar, P K Chidambaran, Ricky C Hetherington: Apparatus for maintaining program correctness while allowing loads to be boosted past stores in an out-of-order machine. Sun Microsystems, William J Kubida, Steven K Hogan & Hartson Barton, May 2, 2000: US06058472 (35 worldwide citation)

A system, apparatus and method for ensuring program correctness in an out-of-order processor spite of younger load instructions being boosted past an older store utilizing a memory disambiguation buffer ("MDB"). The memory disambiguation buffer stores all memory operations that have not yet been ret ...


10
Ramesh Panwar, Deepak Goel, Srinivasan Jagannadhan: Methods and apparatus related to packet classification based on range values. Juniper Networks, Cooley, June 15, 2010: US07738454 (34 worldwide citation)

In one embodiment, a method includes receiving a portion of a hash key vector. The hash key vector can be defined based on a range value and based on at least a portion of an address value from a data packet queued within a multi-stage switch. The method also includes defining, based on the hash key ...