1
Ramesh C Varshney: Wafer level integration technique. Inova Microelectronics Corporation, Townsend and Townsend, October 27, 1987: US04703436 (91 worldwide citation)

Wafer level integration is provided by using individually integrated circuits on a wafer substrate and generating an electrically ordered matrix of functional integrated circuits assigned from a random distribution of functional, partially functional, and non-functional circuits. Each circuit is ind ...


2
Ramesh C Varshney: Test system for segmented memory. Harry M Weiss, January 22, 1985: US04495603 (32 worldwide citation)

A semiconductor memory system is organized into a plurality of segments and is equipped with multiplexed or multifunctional pin for input/output purposes; e.g. the memory address pins, since there is a portion of each memory cycle during which the logic state of the address pins is unimportant. Logi ...


3
Ramesh C Varshney: Method of forming recessed isolation oxide layers. Harry M Weiss, June 9, 1981: US04272308 (26 worldwide citation)

A method of providing recessed oxide isolation layers employs prior art techniques to the point at which a photoetched recess has exposed the semiconductor surface in which the recessed oxide isolation layer is to be grown. The semiconductor wafer is then subjected to a nitride layer formation proce ...


4
Ramesh C Varshney: Serial-parallel-serial charged coupled device memory and a method of transferring charge therein. Fairchild Camera & Instrument, Kenneth Olsen, Henry K Woodward, Carl Silverman, January 8, 1985: US04493060 (23 worldwide citation)

An SPS CCD memory using two phase clocking in the serial registers and ripple clocking in the parallel registers with interlacing transfer of charge in the parallel registers to the output serial registers. First alternate parallel registers are coupled to the output register through first transfer ...


5
Ramesh C Varshney: Semiconductor structure for recessed isolation oxide. Harry M Weiss, July 31, 1984: US04462846 (17 worldwide citation)

A method of providing recessed oxide isolation layers employs prior art techniques to the point at which a photoetched recess has exposed the semiconductor surface in which the recessed oxide isolation layer is to be grown. The semiconductor wafer is then subjected to a nitride layer formation proce ...


6
Ramesh C Varshney, Robert J Strain: Identification of repaired integrated circuits. Fairchild Camera & Instrument, Kenneth Olsen, Robert C Colwell, Carl Silverman, October 30, 1984: US04480199 (17 worldwide citation)

A circuit for providing an identification signal indicative of whether or not an integrated circuit has been repaired includes a circuit which operates at potentials outside the normal range of the integrated circuit. The circuit includes at least one transistor T1 serially connected between a TTL p ...


7
Ramesh C Varshney, Kalyanasundaram Venkateswaran: Sense amplifier for CCD memory. Fairchild Camera and Instrument Corporation, Paul J Winters, Michael J Pollock, Warren M Becker, October 12, 1982: US04354257 (16 worldwide citation)

A sense amplifier for use with a charge coupled device in which capacitive coupled charge is employed with a flip-flop circuit to accelerate sense and readout. Operation of the amplifier is effected with two external clocks and two internally generated clocks.


8
Ramesh C Varshney, Kalyanasundaram Venkateswaran, Gilbert F Amelio: Serial-parallel-serial charge-coupled device memory having interlacing and ripple clocking of the parallel shift registers. Fairchild Camera and Instrument Corporation, Alan H MacPherson, Robert C Colwell, August 21, 1979: US04165541 (16 worldwide citation)

A serial-parallel-serial organized charge-coupled device memory incorporates interlacing and ripple clocking of the parallel shift registers to achieve a high density of bits per unit area. The memory is organized as sixteen 4,096-bit blocks which are randomly accessible. The data in each of the six ...


9
Ramesh C Varshney: Programmable address buffer for partial products. Fairchild Camera & Instrument, Kenneth Olsen, Robert C Colwell, Carl L Silverman, October 9, 1984: US04476546 (10 worldwide citation)

A programmable address buffer for coupling external addresses to a desired pair of internal memory addresses includes A and B address inputs 11 and 12, a B address output 15 coupled to the B address input 12, a first inverter I30 coupled to the B address input and a B address output, a first switch ...


10
Ramesh C Varshney: Redundancy roll call technique. Fairchild Camera & Instrument Corporation, Townsend and Townsend, January 28, 1986: US04567580 (9 worldwide citation)

A disabling circuit 71 responsive to a control signal 81 generated by applying to an IC pin 86 a signal outside the range of normal operating voltages of the device 16. The disabling circuit 71 grounds the output of are dundant address decoder such as 31 to disable a spare element 37 of the device 1 ...