1
Ramanujan K Valmiki, Sandeep Bhatia: Video and graphics system with an MPEG video decoder for concurrent multi-row decoding. Broadcom Corporation, Christie Parker & Hale, October 21, 2003: US06636222 (73 worldwide citation)

A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video ...


2
Ramanujan K Valmiki, Sandeep Bhatia: Video and graphics system with a video transport processor. Broadcom Corporation, Christie Parker & Hale, December 13, 2005: US06975324 (70 worldwide citation)

A video and graphics system includes a data transport processor for receiving compressed data streams, a video transport processor for extracting video data, and an audio decode processor for extracting audio data. The data transport processor provides PCRs to the video transport processor and the a ...


3
Ramanujan K Valmiki, Sathish Kumar: Video and graphics system with MPEG specific data transfer commands. Broadcom Corporation, Christie Parker & Hale, December 9, 2003: US06661422 (65 worldwide citation)

A video and graphics system includes a video decoding system for processing compressed video data. The compressed video data includes MPEG-2 video data containing SDTV video data or HDTV video data. The video decoding system includes a video decoder for processing the compressed video data to genera ...


4
Ramanujan K Valmiki, Sathish Kumar: Video and graphics system with MPEG specific data transfer commands. Broadcom Corporation, McAndrews Held & Malloy, August 14, 2007: US07256790 (23 worldwide citation)

A video and graphics system includes a video decoding system for processing compressed video data. The compressed video data includes MPEG-2 video data containing SDTV video data or HDTV video data. The video decoding system includes a video decoder for processing the compressed video data to genera ...


5
Soorgoli Ashok Halambi, Sarang Ramchandra Shelke, Bhramar Bhushan Vatsa, Dibyapran Sanyal, Nishant Manohar Nakate, Ramanujan K Valmiki, Sai Pramod Kumar Atmakuru, William C Salefski, Vidya Praveen: Compiler method for extracting and accelerator template program. Ash Tankha, IP Legal Services, April 12, 2011: US07926046 (22 worldwide citation)

This invention describes a compilation method of extracting and implementing an accelerator control program from an application source code in a processor based system. The application source code comprises arrays and loops. The input application source code is sequential, with loop, branch and call ...


6
Ramanujan K Valmiki, Sandeep Bhatia: Video and graphics system with an MPEG video decoder for concurrent multi-row decoding. Broadcom Corporation, McAndrews Held & Malloy, December 7, 2010: US07848430 (13 worldwide citation)

A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video ...


7
Ramanujan K Valmiki, Sandeep Bhatia: Video and graphics system with an MPEG video decoder for concurrent multi-row decoding. Broadcom Corporation, McAndrews Held & Malloy, October 2, 2007: US07277099 (8 worldwide citation)

A video and graphics system processes video data including both analog video, e.g., NTSC/PAL/SECAM/S-video, and digital video, e.g., MPEG-2 video in SDTV or HDTV format. The video and graphics system includes a video decoder, which is capable of concurrently decoding multiple SLICEs of MPEG-2 video ...


8
Rajugopal Gubbi, Javaji Sunil Babu, Ramanujan K Valmiki: Method and apparatus for memory optimization in MPE-FEC system. SiRF Technology, Thomas Kayden Horstemeyer & Risley, November 11, 2008: US07451378 (3 worldwide citation)

Systems and methods are provided for processing Multi-Protocol Encapsulation (MPE) under the DVB-H standard. The system includes: (a) a receive buffer having entries organized as columns and rows, the addresses for the entries in the receive buffer being arranged sequentially in column-major order; ...


9
Ramanujan K Valmiki, Ashok Halambi, Madhuri Mandava, Seru Srinivas, Shashank Dabral, Marimuthu Kumar, Bill Safelski: Configurable components for embedded system design. Ash Tankha, Lipton Weinberger & Husick, April 3, 2007: US07200703 (3 worldwide citation)

A system and method of designing an accelerator for a processor-based system. The accelerator design problem is partitioned into a data communicate module design problem and a data compute core module design problem. The hardware design of the data communicate module is achieved through a predetermi ...


10
Shashank Dabral, Ramanujan K Valmiki: Data packing in a 32-bit DMA architecture. Ash Tankha, October 28, 2008: US07444442 (3 worldwide citation)

A method of reducing data transfer overheads in a 32-bit bus interface unit direct memory access architecture. The method comprises the steps of identifying the optimal number of data elements, that can be accessed as a single full-word transfer, setting data packing criteria and analysing the data ...