1
Ramachandra Divakauni, Mark C Hakey, William H L Ma, Jack A Mandelman, William R Tonti: SOI stacked DRAM logic. International Business Machines Corporation, Mark F Chadurjian, Whitman Curtis & Christofferson P C, April 8, 2003: US06544837 (206 worldwide citation)

A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator (SOI) switching transistors and short signal ...


2
Ramachandra Divakauni, Mark C Hakey, William H L Ma, Jack A Mandclman, William R Tonti: SIO stacked DRAM logic. International Business Machines Corporation, Mark F Chadurjian, Whitham Curtis & Christofferson P C, July 8, 2003: US06590258 (130 worldwide citation)

A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator (SOI) switching transistors and short signal ...


3
Ramachandra Divakauni, Mark C Hakey, William H L Ma, Jack A Mandclman, William R Tonti: SOI stacked dram logic. Whitham Curtis & Christofferson PC, March 28, 2002: US20020036322-A1 (1 worldwide citation)

A composite, layered, integrated circuit formed by bonding of insulator layers on wafers provides for combination of otherwise incompatible technologies such as trench capacitor DRAM arrays and high performance, low power, low voltage silicon on insulator (SOI) switching transistors and short signal ...