1
Katherina Babich
Deok kee Kim, Kenneth T Settlemyer Jr, Kangguo Cheng, Ramachandra Divakaruni, Carl J Radens, Dirk Pfeiffer, Timothy Dalton, Katherina Babich, Arpan P Mahorowala, Harald Okorn Schmidt: Methods and structures for protecting one area while processing another area on a chip. International Business Machines Corporation, Whitman Curtis Christofferson & Cook PC, Joseph P Abate, March 3, 2009: US07497959 (4 worldwide citation)

Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided whi ...


2
Katherina Babich
Deok kee Kim, Kenneth T Settlemyer, Kangguo Cheng, Ramachandra Divakaruni, Carl J Radens, Dirk Pfeiffer, Thimothy Dalton, Katherina Babich, Arpan P Mahorowala, Harald Okorn Schmidt: Methods and structures for protecting one area while processing another area on a chip. Whitham Curtis & Christofferson PC, October 23, 2008: US20080261128-A1

Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided whi ...


3
Katherina Babich
Deok kee Kim, Kenneth T Settlemyer, Kangguo Cheng, Ramachandra Divakaruni, Carl J Radens, Dirk Pfeiffer, Timothy Dalton, Katherina Babich, Arpan P Mahorowala, Harald Okorn Schmidt: Methods and structures for protecting one area while processing another area on a chip. International Business Machines Corporation, Whitham Curtis & Christofferson PC, November 17, 2005: US20050255386-A1

Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided whi ...


4
James W Adkisson, Ramachandra Divakaruni, Jeffrey P Gambino, Jack A Mandelman: Embedded DRAM on silicon-on-insulator substrate. International Business Machines Corporation, William D Sabo, Schmeiser Olsen & Watts, February 26, 2002: US06350653 (131 worldwide citation)

A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions and logic devices are formed in silicon-on-insulator (“SOI”) regions and where buried, doped glass is used ...


5
James W Adkisson, Ramachandra Divakaruni, Jeffrey P Gambino, Jack A Mandelman: Semiconductor device of an embedded DRAM on SOI substrate. International Business Machines Corporation, William D Sabo, Schmeiser Olsen & Watts, July 8, 2003: US06590259 (130 worldwide citation)

A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions and logic devices are formed in silicon-on-insulator (“SOI”) regions and where buried, doped glass is used ...


6
Ramachandra Divakaruni, Russell J Houghton, Jack A Mandelman, W David Pricer, William R Tonti: Method for novel SOI DRAM BICMOS NPN. International Business Machines Corporation, Mark F Chadurjian, Eugene I Shkurko, F William McLaughlin, December 10, 2002: US06492211 (124 worldwide citation)

There is disclosed herein a unique fabrication sequence and the structure of a vertical silicon on insulator (SOI) bipolar transistor integrated into a typical DRAM trench process sequence. A DRAM array utilizing an NFET allows for an integrated bipolar NPN sequence. Similarly, a vertical bipolar PN ...


7

8
Jochen Beintner, Gary B Bronner, Ramachandra Divakaruni, Yujun Li: Process for fabrication of FinFETs. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Ido Tuchman, December 30, 2008: US07470570 (103 worldwide citation)

A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the ...


9
James W Adkisson, Arne W Ballantine, Ramachandra Divakaruni, Jeffrey B Johnson, Erin C Jones, Hon Sum P Wong: Method for making multiple threshold voltage FET using multiple work-function gate materials. International Business Machines Corporation, Robert Curcio, Richard A Henkler, DeLio & Peterson, September 28, 2004: US06797553 (86 worldwide citation)

A shorter gate length FET for very large scale integrated circuit chips is achieved by providing a wafer with multiple threshold voltages. Multiple threshold voltages are developed by combining multiple work function gate materials. The gate materials are geometrically aligned in a predetermined pat ...


10
Paul D Agnello, Arne W Ballantine, Ramachandra Divakaruni, Erin C Jones, Edward J Nowak, Jed H Rankin: Vertical trench-formed dual-gate FET device structure and method for creation. International Business Machines Corporation, Kelly M Reynolds, Mark F Chadururjian, DeLio & Peterson, June 18, 2002: US06406962 (56 worldwide citation)

The present invention relates to an apparatus and method of forming one or more FETs having a vertical trench-formed double-gate, with a plurality of nitride layers having oxide marker etch-stop layers provided periodically there-through, thereby adapting the FETs to have a plurality of selectable g ...



Click the thumbnails below to visualize the patent trend.