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Michael Patrick Chudzik, Robert H Dennard, Rama Divakaruni, Bruce Kenneth Furman, Rajarao Jammy, Chandrasekhar Narayan, Sampath Purushothaman, Joseph F Shepard Jr, Anna Wanda Topol: High density chip carrier with integrated passive devices. Internation Business Machines Corporation, Daniel P Morris Esq, Perman & Green, April 18, 2006: US07030481 (256 worldwide citation)

A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.


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Michael Patrick Chudzik, Robert H Dennard, Rama Divakaruni, Bruce Kenneth Furman, Rajarao Jammy, Chandrasekhar Narayan, Sampath Purushothaman, Joseph F Shepard Jr, Anna Wanda Topol: High density chip carrier with integrated passive devices. International Business Machines Corporation, Daniel P Morris, Perman & Green, November 8, 2005: US06962872 (243 worldwide citation)

A carrier for a semiconductor component is provided having passive components integrated in its substrate. The passive components include decoupling components, such as capacitors and resistors. A set of connections is integrated to provide a close electrical proximity to the supported components.


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Jack A Mandelman, Rama Divakaruni, William R Tonti: Shared body and diffusion contact structure and method for fabricating same. International Business Machines Corporation, Schmeiser Olsen & Watts, August 6, 2002: US06429477 (154 worldwide citation)

The preferred embodiment overcomes the difficulties found in the background art by providing a body contact and diffusion contact formed in a single shared via for silicon on insulator (SOI) technologies. By forming the body contact and diffusion contact in a single shared via, device size is minimi ...


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James W Adkisson, Paul D Agnello, Arne W Ballantine, Rama Divakaruni, Erin C Jones, Jed H Rankin: Double gate trench transistor. International Business Machines Corporation, Mark F Chadurjian, Whitham Curtis & Christofferson P C, October 29, 2002: US06472258 (94 worldwide citation)

A field effect transistor is formed with a sub-lithographic conduction channel and a dual gate which is formed by a simple process by starting with a silicon-on-insulator wafer, allowing most etching processes to use the buried oxide as an etch stop. Low resistivity of the gate, source and drain is ...


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Rama Divakaruni, Louis C Hsu, Rajiv V Joshi, Carl J Radens: High performance FET with elevated source/drain region. International Business Machines, Law Office of Charles W Peterson Jr, Louis J Percello, March 8, 2005: US06864540 (62 worldwide citation)

The invention includes a field effect transistor (FET) on an insulator layer, and integrated circuit (IC) on SOI chip including the FETs and a method of forming the IC. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin si ...


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Rama Divakaruni, Jeffrey P Gambino, Jack A Mandelman, Rajesh Rengarajan: Transistors having independently adjustable parameters. International Business Machines Corporation, Infineon Technologies, Todd M C Li, Ratner & Prestia, December 31, 2002: US06501131 (48 worldwide citation)

The process rules for manufacturing semiconductor devices such as MOSFET's are modified to provide dual work-function doping following the customary gate sidewall oxidation step, greatly reducing thermal budget and boron penetration concerns. The concern of thermal budget is further significant ...


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Rama Divakaruni, Stephan Kudelka, Helmut Tews, Irene McStay, Kil Ho Lee, Uwe Schroeder: Negative ion implant mask formation for self-aligned, sublithographic resolution patterning for single-sided vertical device formation. International Business Machines Corporation, Infineon Technologies, H Daniel Schmurmann, Graham S Jones II, December 24, 2002: US06498061 (34 worldwide citation)

A process for fabricating a single-sided semiconductor deep trench structure filled with polysilicon trench fill material includes the following steps. Form a thin film, silicon nitride, barrier layer over the trench fill material. Deposit a thin film of an amorphous silicon masking layer over the b ...


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Rama Divakaruni, Gregory Freeman, Marwan Khater, William Tonti: Structure and method of forming a bipolar transistor having a void between emitter and extrinsic base. International Business Machines Corporation, Daryl K Neff, H Daniel Schnurmann, September 6, 2005: US06940149 (28 worldwide citation)

Structure and a method are provided for making a bipolar transistor, the bipolar transistor including a collector, an intrinsic base overlying the collector, an emitter overlying the intrinsic base, and an extrinsic base spaced from the emitter by a gap, the gap including at least one of an air gap ...


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Jochen Beintner, Rama Divakaruni, Rajarao Jammy: Nitrided STI liner oxide for reduced corner device impact on vertical device performance. International Business Machines Corporation, DeLio & Peterson, Peter W Peterson, Todd M C Li, February 14, 2006: US06998666 (26 worldwide citation)

A method of fabricating an integrated circuit device comprises etching a trench in a substrate and forming a dynamic random access memory (DRAM) cell having a storage capacitor at a lower end and an overlying vertical metal oxide semiconductor field effect transistor (MOSFET) comprising a gate condu ...