1
Hong Wang, Ralph Kling, Yong Fong Lee, David A Berson, Michael A Kozuch, Konrad Lai: Processing essential and non-essential code separately. Intel Corporation, Schwegman Lundberg Woessner & Kluth P A, March 28, 2006: US07020766 (18 worldwide citation)

A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion ...


2
Hong Wang, Perry Wang, Ralph Kling, Neil A Chazin, John Shen: Quantization and compression for computation reuse. Intel Corporation, Schwegman Lundberg Woessner & Kluth P A, June 27, 2006: US07069545 (17 worldwide citation)

Software reuse instances are found from an execution trace through a process of quantization, discovery, and synthesis. Quantization includes mapping n-dimensional vectors that correspond to instructions, live-in states, and live-out states to one dimensional symbols, and arranging the symbols into ...


3
Hong Wang, Ralph Kling, Edward T Grochowski, Kalpana Ramakrishnan: Presbyopic branch target prefetch method and apparatus. Intel Corporation, Schwegman Lundberg Woessner & Kluth P A, May 4, 2004: US06732260 (10 worldwide citation)

An instruction prefetch apparatus includes a branch target buffer (BTB), a presbyopic target buffer (PTB) and a prefetch stream buffer (PSB). The BTB includes records that map branch addresses to branch target addresses, and the PTB includes records that map branch target addresses to subsequent bra ...


4
Hong Wang, Christopher J Hughes, Ralph Kling, Yong Fong Lee, Daniel M Lavery, John Shen, Jamison Collins: Register rotation prediction and precomputation. Intel Corporation, Schwegman Lundberg Woessner & Kluth P A, May 23, 2006: US07051193 (8 worldwide citation)

Instruction-level parallelism in software pipelined loops is exploited by predicting future register rotations. A processor includes an architected current frame marker register and at least one unarchitected frame marker register. Register rotation prediction is achieved by setting the register rot ...


5
Hong Wang, Ralph Kling, Jeff Baxter, Konrad Lai: Method and apparatus for access demarcation. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 14, 2003: US06507895 (8 worldwide citation)

An embodiment of the present invention provides for an apparatus for memory access demarcation. Data is accessed from a first cache, which comprises a first set of addresses and corresponding data at each of the addresses in the first set. A plurality of addresses is generated for a second set of ad ...


6
Ralph Kling, Jeffrey D Chamberlain, Perry H Wang: Method and apparatus for processing a predicated instruction using limited predicate slip. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 19, 2005: US06883089 (4 worldwide citation)

A system and method of processing a predicated instruction is disclosed. A consumer instruction and a predicated instruction are received in an reservation station of an out-order processor. The consumer instruction depends on a result of the predicated instruction. The predicated instruction is dis ...


7
Thomas Y Yeh, Hong Wang, Ralph Kling, Yong Fong Lee: Optimal redundant arithmetic for microprocessors design. Intel Corporation, David N Tran, January 25, 2005: US06848043 (2 worldwide citation)

Methods and apparatus for improving system performance using redundant arithmetic are disclosed. In one embodiment, one or more dependency chains are formed. A dependency chain may comprise of two or more instructions. A first instruction may generate a result in a redundant form. A second instructi ...


8
Hong Wang, Ralph Kling, Edward T Grochowski, Kalpana Ramakrishnan: Presbyopic branch target prefetch method and apparatus. Intel Corporation, Schwegman Lundberg & Woessner P A, April 7, 2009: US07516312 (2 worldwide citation)

An instruction prefetch apparatus includes a branch target buffer (BTB), a presbyopic target buffer (PTB) and a prefetch stream buffer (PSB). The BTB includes records that map branch addresses to branch target addresses, and the PTB includes records that map branch target addresses to subsequent bra ...


9
Hong Wang, Ralph Kling, Yong Fong Lee, David A Berson, Michael A Kozuch, Konrad Lai: Identifying and processing essential and non-essential code separately. Intel Corporation, Schwegman Lundberg & Woessner P A, October 14, 2008: US07437542 (2 worldwide citation)

A conjugate processor includes an instruction set architecture (ISA) visible portion having a main pipeline, and an h-flow portion having an h-flow pipeline. The binary executed on the conjugate processor includes an essential portion that is executed on the main pipeline and a non-essential portion ...


10
Hong Wang, Ralph Kling, Edward T Grochowski, Kalpana Ramakrishnan: Presbyopic branch target prefetch method and apparatus. Intel Corporation, Schwegman Lundberg Woessner & Kluth Pa, September 30, 2004: US20040193856-A1

An instruction prefetch apparatus includes a branch target buffer (BTB), a presbyopic target buffer (PTB) and a prefetch stream buffer (PSB). The BTB includes records that map branch addresses to branch target addresses, and the PTB includes records that map branch target addresses to subsequent bra ...