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Joseph C Circello, Richard H Duerden, Roger W Luce, Ralph H Olson: Pipelined system for reducing instruction access time by accumulating predecoded instruction bits a FIFO. Edgcore Technology, Cahill Sutton & Thomas, March 31, 1992: US05101341 (111 worldwide citation)

A system and technique for providing early decoding of complex instructions in a pipelined processor uses a programmed logic array to decode instruction segments and loads both the instruction bits and the associated predecoded bits into a FIFO buffer to accumulate a plurality of such entries. Meanw ...


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Joseph C Circello, Richard H Duerden, Roger W Luce, Ralph H Olson: Method and system for executing pipelined three operand construct. Edgcore Technology, Cahill Sutton & Thomas, July 14, 1992: US05131086 (32 worldwide citation)

A system and technique for providing early decoding of complex instructions in a pipelined processor uses a programmed logic array to decode instruction segments and loads both the instruction bits and the associated predecoded bits into a FIFO buffer to accumulate a plurality of such entries. Meanw ...


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