1
Rakesh H Patel, John E Turner, Myron W Wong: Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements. Altera Corporation, Robert R Jackson, G Victor Treyz, December 6, 1994: US05371422 (225 worldwide citation)

A programmable logic device is provided that has a two-dimensional array of logic array blocks. The logic array blocks, which contain advanced macrocells, contain programmable input arrays based on pterm logic and are two-dimensionally interconnected with global horizontal and vertical conductors. T ...


2
Rakesh H Patel: Macrocell with flexible product term allocation. Altera Corporation, Robert R Jackson, G Victor Treyz, September 27, 1994: US05350954 (168 worldwide citation)

An improved macrocell is provided for summing product term inputs to complete a sum of products. Some or all of a macrocell's product terms can be allocated to another macrocell. The macrocell OR function remains available to sum product term inputs, even when other product term inputs in the same m ...


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John C Costello, Rakesh H Patel: Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers. Altera Corporation, G Victor Treyz, Robert R Jackson, Fish & Neave, January 9, 1996: US05483178 (155 worldwide citation)

A programmable logic device is provided that contains a plurality of logic array blocks arranged in rows and columns. The logic array blocks are interconnected with horizontal conductors in each row and vertical conductors in each column. The logic array blocks and the interconnections between condu ...


5
Christopher J Pass, James D Sansbury, Raminda U Madurawe, John E Turner, Rakesh H Patel, Peter J Wright: Programmable interconnect junction. Altera Corporation, Townsend & Townsend and Crew, September 7, 1999: US05949710 (118 worldwide citation)

A static, nonvolatile, and reprogrammable programmable interconnect junction cell for implementing programmable interconnect in an integrated circuit. The programmable interconnect junction (600) is programmably configured to couple or decouple a first interconnect line (210) and a second interconne ...


6
Rakesh H Patel, Kevin A Norman: Partially reconfigurable programmable logic device. Altera Corporation, Townsend and Townsend and Crew, February 1, 2000: US06020758 (111 worldwide citation)

Various embodiments of a programmable logic device (PLD) capable of being dynamically partially reconfigured are disclosed. The PLD provides circuitry for changing its configuration data in whole or in part without halting the operation nor losing any of the logic state of the PLD. In one embodiment ...


7
Stephen P Sample, Michael R Butts, Kevin A Norman, Rakesh H Patel: I/O buffer circuit with pin multiplexing. Altera Corporation, Quickturn Design Systems, Lyon & Lyon, February 1, 2000: US06020760 (105 worldwide citation)

An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has flexible input/output buffer circuits. These input/output buffer circuits transfer data either bidirectionally or unidirectionally between an input/output pin and a ...


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Stephen P Sample, Michael R Butts, Kevin A Norman, Rakesh H Patel: I/O buffer circuit with pin multiplexing. Altera Corporation, Quickturn Design Systems, Townsend and Townsend and Crew, September 4, 2001: US06285211 (81 worldwide citation)

An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array (“FPGA”), as described herein has flexible input/output buffer circuits. These input/output buffer circuits transfer data either bidirectionally or unidirectionally between an input/output pin and a ...


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Tony K Ngai, Rakesh H Patel, Srinivas T Reddy, Richard G Cliff: Programmable logic device having embedded dual-port random access memory configurable as single-port memory. Altera Corporation, Jeffrey H Ingerman, Fish & Neave, October 15, 2002: US06467017 (78 worldwide citation)

A programmable logic device has embedded random access memory (“RAM”) that can function equally well in either single-port or dual-port operation. The RAM is dual-port RAM whose read address inputs and write address inputs are both connected to a conductor bus via two different sparsely populated pr ...


10
Rakesh H Patel, Myron W Wong: Programmable logic device with redundant circuitry. Altera Corporation, Robert R Jackson, G Victor Treyz, November 29, 1994: US05369314 (72 worldwide citation)

A programmable logic device is provided that has redundant circuitry. When a portion of the programmable logic device circuitry is found to be defective, the redundant circuitry is switched into use in place of the defective circuitry by programming appropriate portions of the circuitry of the progr ...