1
Rajiv Gupta, Prasad Raje: Microprocessor having software controllable power consumption. Hewlett Packard Company, November 30, 1999: US05996083 (239 worldwide citation)

A microprocessor is provided which includes a power control register for controlling the rate of execution and therefore the power consumption of individual functional units. The power control register includes a plurality of fields corresponding to the functional units for storing values that contr ...


2
Harshvardhan Sharangpani, Rajiv Gupta, Judge K Arora: Method for detecting thread switch events. Intel Corporation, Hewlette Packard, Leo V Novakoski, August 7, 2001: US06272520 (102 worldwide citation)

A method for detecting thread switch conditions provides first and second scoreboard bits for each register in a register file. The first scoreboard bit associated with a register is set when a load is generated to return data to the register. The second scoreboard bit is set if the load misses in a ...


3
Marcelo Weinberger, Tomas G Rokicki, Gadiel Seroussi, Rajiv Gupta, Neri Merhav, Joesp M Ferrandiz: Optimizing computer performance by using data compression principles to minimize a loss function. Hewlett Packard Company, September 17, 2002: US06453389 (85 worldwide citation)

The method of prefetching data into cache to minimize CPU stall time uses a rough predictor to make rough predictions about what cache lines will be needed next by the CPU. The address difference generator uses the rough prediction and the actual cache miss address to determine the address differenc ...


4
Rajiv Gupta, William S Worley Jr: Out-of-order execution using encoded dependencies between instructions in queues to determine stall values that control issurance of instructions from the queues. Hewlett Packard Company, August 24, 1999: US05941983 (76 worldwide citation)

A method for executing instructions out-of-order to improve performance of a processor includes compiling the instructions of a program into separate queues along with encoded dependencies between instructions in the different queues. The processor then issues instructions from each of these queues ...


5
Alan H Karp, Rajiv Gupta: Sectored virtual memory management system and translation look-aside buffer (TLB) for the same. Hewlett Packard Company, August 31, 1999: US05946716 (75 worldwide citation)

A memory management system is described which divides each virtual page into two or more sectors. Each of these sectors can then be individually loaded into memory in order to reduce bandwidth consumed loading virtual pages into a physical memory. A TLB for this system includes a plurality of TLB en ...


6
Alexander H Slocum Jr, Rajiv Gupta, Stephen E Jones, Alexander H Slocum Sr: Method and apparatus for characterizing the temporal resolution of an imaging device. The General Hospital Corporation, Quarles & Brady, January 4, 2011: US07863897 (71 worldwide citation)

A system and method for determining the temporal resolution of a tomographic imaging device uses an apparatus to drive one or more dynamic phantoms composed of multiple materials. The apparatus is placed at or near the isocenter of the imaging device and the one or more phantoms are moved to produce ...


7
Eugene R Worley, Addison B Jones, Rajiv Gupta: ESD protection for submicron CMOS circuits. Rockwell International Corporation, H Frederick Hamann, George A Montanye, Philip K Yu, August 8, 1995: US05440162 (70 worldwide citation)

An ESD protection circuit for the pads of an integrated circuit (IC) using silicide-clad diffusions is disclosed. The circuit uses a robust N+ diode with N-well block, an output NFET and a large transient clamp, each with a distributed, integrated N-well drain resistor to prevent the IC from avalanc ...


8
Alan H Karp, Rajiv Gupta, Arindam Banerji, Ernest Mak, Sandeep Kumar, Guillermo Rozas, Chia Chiang Chao, Venkatesh Krishnan, Alexandre Bronstein: Infrastructure for an open digital services marketplace. Hewlett Packard Company, March 20, 2001: US06205466 (56 worldwide citation)

A software infrastructure for providing an open digital services marketplace including a naming manager that enables a requesting task to refer to a desired resource using a name which is local to the requesting task and a router that forwards the request to an appropriate handler for the desired re ...


9
Robert Aglietti, Rajiv Gupta: Cache management for a multi-threaded processor. Hewlett Packard Company, April 30, 2002: US06381676 (55 worldwide citation)

A method and apparatus which provides a cache management policy for use with a cache memory for a multi-threaded processor. The cache memory is partitioned among a set of threads of the multi-threaded processor. When a cache miss occurs, a replacement line is selected in a partition of the cache mem ...


10
Rajiv Gupta: Method of synchronizing parallel processors employing channels and compiling method minimizing cross-processor data dependencies. North American Philips Corporation, Jack D Slobod, May 31, 1994: US05317734 (51 worldwide citation)

A method of synchronizing the parallel processors of a multiple instruction stream multiprocessor employs a limited number of register channels, which may be re-used, for enforcing cross-stream data or event dependencies by passing data or event notifications in a synchronizing fashion. Cross-stream ...