1
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard Uhlig, Larry Smith, Dion Rodgers: Extended paging tables to map guest physical memory addresses from virtual memory page tables to host physical memory addresses in a virtual machine system. Intel Corporation, Thomas R Lane, February 8, 2011: US07886126 (16 worldwide citation)

A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a referenc ...


2
Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard A Uhlig, Udo Steinberg, Sebastian Schoenberg, Sridhar Muthrasanallur, Steven M Bennett, Andrew V Anderson, Erik C Cota Robles: Delivering interrupts directly to a virtual processor. Intel Corporation, Trop Pruner & Hu P C, October 9, 2012: US08286162 (15 worldwide citation)

Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the i ...


3
Rajesh Sankaran Madukkarumukumana, Gilbert Neiger, Ohad Falik, Sridhar Muthrasanallur, Gideon Gerzon: Posting interrupts to virtual processors. Intel Corporation, Thomas R Lane, October 22, 2013: US08566492 (8 worldwide citation)

Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data struct ...


4
Rajesh Sankaran Madukkarumukumana, Sridhar Muthrasanallur, Ramakrishna Huggahalli, Rameshkumar G Illikkal: Performing direct cache access transactions based on a memory access data structure. Thomas R Lane, May 3, 2011: US07937534 (6 worldwide citation)

Embodiments of an apparatus, method, and system for encoding direct cache access transactions based on a memory access data structure are disclosed. In one embodiment, an apparatus includes memory access logic and transaction logic. The memory access logic is to determine whether to allow a memory a ...


5
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard Uhlig, Larry Smith, Dion Rodgers: Virtualizing physical memory in a virtual machine system utilizing multilevel translation table base registers to map guest virtual addresses to guest physical addresses then to host physical addresses. Intel Corporation, Thomas R Lane, February 4, 2014: US08645665 (5 worldwide citation)

A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a referenc ...


6
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard Uhlig, Larry Smith, Dion Rodgers: Translating a guest virtual address to a host physical address as guest software executes on a virtual machine. Intel Corporation, Thomas R Lane, September 10, 2013: US08533428 (4 worldwide citation)

A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a referenc ...


7
Rajesh Sankaran Madukkarumukumana, Gilbert Neiger, Ohad Falik, Sridhar Muthrasanallur, Gideon Gerzon: Posting interrupts to virtual processors. Intel Corporation, Thomas R Lane, September 23, 2014: US08843683 (2 worldwide citation)

Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data struct ...


8
Rajesh Sankaran Madukkarumukumana, Gilbert Neiger, Ohad Falik, Sridhar Muthrasanallur, Gideon Gerzon: Posting interrupts to virtual processors. Intel Corporation, Thomas R Lane, August 25, 2015: US09116869 (2 worldwide citation)

Embodiments of systems, apparatuses, and methods for posting interrupts to virtual processors are disclosed. In one embodiment, an apparatus includes look-up logic and posting logic. The look-up logic is to look-up an entry associated with an interrupt request to a virtual processor in a data struct ...


9
Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard A Uhlig, Udo Steinberg, Sebastian Schoenberg, Sridhar Muthrasanallur, Steven M Bennett, Andrew V Anderson, Erik C Cota Robles: Delivering interrupts directly to a virtual processor. Intel Corporation, Trop Pruner & Hu P C, January 20, 2015: US08938737 (1 worldwide citation)

Embodiments of apparatuses, methods, and systems for delivering an interrupt to a virtual processor are disclosed. In one embodiment, an apparatus includes an interface to receive an interrupt request, delivery logic, and exit logic. The delivery logic is to determine, based on an attribute of the i ...


10
Steven M Bennett, Andrew V Anderson, Gilbert Neiger, Rajesh Sankaran Madukkarumukumana, Richard UhligQ, Lawrence Smith III, Scott D Rodgers: Virtualizing physical memory in a virtual machine system using a hierarchy of extended page tables to translate guest-physical addresses to host-physical addresses. Intel Corporation, Nicholson De Vos, Webster & Elliott, October 30, 2018: US10114767

A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a referenc ...