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Rajan Suresh Natarajan, Smith Michael John Sebastian, Schakel Keith R, Wang David T, Weber Frederick Daniel: Memory circuit system and method. Rajan Suresh Natarajan, Smith Michael John Sebastian, Schakel Keith R, Wang David T, Weber Frederick Daniel, Metaram, KOTAB Dominic M, August 23, 2007: WO/2007/095080 (76 worldwide citation)

A memory circuit system and method are provided. In one embodiment, an interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints ...


2
Rajan Suresh, Smith Michael, Wang David: Methods and apparatus of stacking drams. Metaram, Rajan Suresh, Smith Michael, Wang David, ZILKA Kevin J, March 8, 2007: WO/2007/028109 (71 worldwide citation)

Large capacity memory systems (FB-DIMMs) are constructed using stacked memory integrated circuits (220) or chips (310). The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.


3
Rajan Suresh N: An integrated memory core and memory interface circuit. Metaram, Rajan Suresh N, STATTLER John, January 4, 2007: WO/2007/002324 (19 worldwide citation)

A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing op ...


4
Rajan Suresh Natarajan, Schakel Keith R, Smith Michael John Sebastian, Wang David T, Weber Frederick Daniel: Memory circuit system and method. Metaram, Rajan Suresh Natarajan, Schakel Keith R, Smith Michael John Sebastian, Wang David T, Weber Frederick Daniel, ZILKA Kevin J, May 29, 2008: WO/2008/063251 (10 worldwide citation)

A memory circuit system (Figure 1) and method are provided in the context of various embodiments. In one embodiment, an interface circuit (102) remains in communication with a plurality of memory circuits (104) and a system. The interface circuit is operable to interface the memory circuits and the ...


5
Wilsher Kenneth R, Lo William K, Rajan Suresh N: Dual-laser voltage probing of ics. Schlumberger Technologies, September 16, 1998: EP0864872-A2 (4 worldwide citation)

A probe beam is used to sample the waveform on an IC device under test (DUT) during each cycle of a test pattern applied to the DUT. A reference laser beam is also used to sample the DUT. For each cycle of the test pattern, the reference and probe beams sample the DUT at the same physical location, ...


6
Rajan Suresh N, Kanai Kenichi: Predictive waveform acquisition. Schlumberger Technologies, December 11, 1996: EP0747716-A2 (3 worldwide citation)

A tester exercises a DUT with a repetitive signal pattern, supplying a trigger signal for each repetition. The waveform on a conductor of the DUT is to be acquired by repeatedly measuring voltage at each of a number of sample points following the trigger, using a charged-particle probe system having ...


7
RAJAN SURESH NATARAJAN, SMITH MICHAEL JOHN SEBASTIAN, SCHAKEL KEITH R, WANG DAVID T, WEBER FREDERICK DANIEL: Memory circuit system and method, Speicherschaltungssystem und -Verfahren, Système et procédé de circuit de mémoire. GOOGLE, May 30, 2012: EP2458505-A1 (2 worldwide citation)

A memory circuit system and method are provided. In one embodiment, an interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints ...


8
RAJAN SURESH NATARAJAN, SMITH MICHAEL JOHN SEBASTIAN, SCHAKEL KEITH R, WANG DAVID T, WEBER FREDERICK DANIEL: Memory circuit system and method, Speicherschaltungssystem und -Verfahren, Système et procédé de circuit de mémoire. GOOGLE, May 9, 2012: EP2450798-A1 (1 worldwide citation)

A memory circuit system and method are provided. In one embodiment, an interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints ...


9
Rajan Suresh N: An integrated memory core and memory interface circuit. Metaram, March 12, 2008: GB2441726-A (1 worldwide citation)

A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing op ...


10
RAJAN SURESH NATARAJAN , SMITH MICHAEL JOHN SEBASTIAN , SCHAKEL KEITH R , WANG DAVID T , WEBER FREDERICK DANIEL : [fr] Système et procédé de circuit de mémoire, [de] Speicherschaltungssystem und -Verfahren, [en] Memory circuit system and method. GOOGLE  , March 12, 2014: EP2706461-A1

[en] A memory circuit system and method are provided. In one embodiment, an interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constr ...



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