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Glenn Hinton, Madhavan Parthasarathy, Rajesh Parthasarathy, Muthukumar Swaminathan, Raj Ramanujan, David Zimmerman, Larry O Smith, Adrian C Moga, Scott J Cape, Wayne A Downer, Robert S Chappell: Apparatus, method, and system for implementing micro page tables. Intel Corporation, Schwabe Williamson & Wyatt P C, September 16, 2014: US08838935 (41 worldwide citation)

In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address t ...


2
Raj Ramanujan: Apparatus and method for ensuring that lock requests are serviced in a multiprocessor system. Digital Equipment Corporation, Richard J Paciulan, Denis C Maloney, August 23, 1994: US05341491 (41 worldwide citation)

A lockout avoidance circuit is provided for a plurality of nodes which generate lock requests for a shared resource such as a memory location. The circuit insures that lock requests are eventually satisfied. A lock queue includes a plurality of registers pipelined together. Lock requests only enter ...


3
Raj Ramanujan, James B Keller, William A Samaras, John Derosa, Robert E Stewart: High speed bus system that incorporates uni-directional point-to-point buses. Hewlett Packard Development Company, August 9, 2005: US06928500 (21 worldwide citation)

A high speed bus system for use in a shared memory system that allows for the high speed transmissions of commands and data between a number of processors and a memory array of a multi-processor, shared memory system, with the high speed bus system including a central unit and a series of uni-direct ...


4
Raj Ramanujan, James B Keller, Jay Stickney, Steven Ho, Paul Lemmon: Method of controlling a shared memory bus in a multiprocessor system for preventing bus collisions and for ensuring a full bus. Digital Equipment Corporation, Kenyon & Kenyon, April 13, 1993: US05202973 (21 worldwide citation)

A system and method for controlling a shared memory bus in a computer of a multi-processor system prevents collisions on the shared bus and ensures that the bus is full at system start-up. Steady state operations are maintained without the need for a queuing mechanism in the system's memory controll ...


5
Paul J Lemmon, Raj Ramanujan, Jay C Stickney: Method and apparatus for the dynamic adjustment of data transfer timing to equalize the bandwidths of two buses in a computer system having different bandwidths. Digital Equipment Corporation, Kenyon & Kenyon, January 11, 1994: US05278974 (18 worldwide citation)

The bandwidth of a first bus and a second bus, unequal due to differences in protocol overheads and cycle times between the buses, are equalized without sacrificing any bandwidth on the lower bandwidth bus and without introducing any buffering in a control logic device. The control logic device equa ...


6
John H Zurawski, Raj Ramanujan, John De Rosa: Method and apparatus for sharing data between processors in a computer system. Digital Equipment Corporation, Kenyon & Kenyon, November 16, 1993: US05263144 (17 worldwide citation)

A cache coherency scheme in a multiprocessor computer system allows data sharing between caches at a fast rate. A new cache coherency state is introduced which allows a processor pair to more effectively share data and eliminate bus transfers thereby improving system throughput. The transfer of data ...


7
Paul J Lemmon, Raj Ramanujan: Interleaving read and write operations on a bus and minimizing buffering on a memory module in a computer system. Hewlett Packard Development Company, October 19, 2004: US06807609 (14 worldwide citation)

A computer system is adapted to transfer write data from a central processing unit to one of a plurality of memory modules in a memory array by transferring a block of write data to a memory control logic device. The memory control logic device transfers the block of data in a plurality of data burs ...


8
Raj Ramanujan, James B Keller, William A Samaras, John DeRosa, Robert E Stewart: High speed bus system that incorporates uni-directional point-to-point buses. Hewlett Packard Development Company, February 23, 2010: US07668997 (4 worldwide citation)

An apparatus comprises a plurality of ports wherein each port is adapted to couple to a device. At least one port connects by way of first and second unidirectional, point-to-point communication links with a device. The first unidirectional, point-to-point communication link transfers data from the ...


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Raj Ramanujan, James B Keller, William A Samaras, John De Rosa, Robert E Stewart: High speed bus system that incorporates uni-directional point-to-point buses. Hewlett Packard Development Company, Hewlett Packard Company, October 20, 2005: US20050232287-A1

An apparatus comprises a plurality of ports wherein each port is adapted to couple to a device. At least one port connects by way of first and second unidirectional, point-to-point communication links with a device. The first unidirectional, point-to-point communication link transfers data from the ...


10
Glenn Hinton, Madhavan Parthasarathy, Rajesh Parthasarathy, Muthukumar Swaminathan, Raj Ramanujan, David Zimmerman, Larry O Smith, Adrian C Moga, Scott J Cape, Wayne A Downer, Robert S Chappell: Apparatus, method, and system for implementing micro page tables. March 29, 2012: US20120079232-A1

An apparatus, method, machine-readable medium, and system are disclosed. In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside ...