1
Rahul Razdan, Michael D Smith: Hardware extraction technique for programmable reduced instruction set computers. President and Fellows of Harvard College, Digital Equipment Corporation, Diane C Drozenski, Ronald C Hudgens, October 6, 1998: US05819064 (63 worldwide citation)

A new class of purpose computers called Programmable Reduced Instruction Set Computers (PRISC) use RISC techniques a basis for operation. In addition to the conventional RISC instructions, PRISC computers provide hardware programmable resources which can be configured optimally for a given user appl ...


2
Stephen Van Doren, Rahul Razdan: Distributed data dependency stall mechanism. Compaq Computer Corporation, Hamilton Brook Smith & Reynolds P C, July 4, 2000: US06085294 (58 worldwide citation)

A method and apparatus for preventing system wide data dependent stalls is provided. Requests that reach the top of a probe queue and which target data that is not contained in an attached cache memory subsystem, are stalled until the data is filled into the appropriate location in cache memory. Onl ...


3
Rahul Razdan, Bill Grundmann, Michael D Smith: Dynamically programmable reduced instruction set computer with programmable processor loading on program number field and program number register contents. Digital Equipment Corporation, David A Dagg, Gary E Ross, Arthur W Fisher, December 9, 1997: US05696956 (53 worldwide citation)

A new class of general purpose computers called Programmable Reduced Instruction Set Computers (PRISC) use RISC techniques a basis for operation. In addition to the conventional RISC instructions, PRISC computers provide hardware programmable resources which can be configured optimally for a given u ...


4
Richard Eugene Kessler, Rahul Razdan, Edward John Mclellan: Method and apparatus for delaying the execution of dependent loads. Compaq Information Technologies Group, Hamilton Brook Smith & Reynolds P C, October 8, 2002: US06463523 (40 worldwide citation)

Load/store execution order violations in an out-of-order processor are reduced by determining whether a source address of a load instruction is the same as a destination address of a store instruction on which execution the load instruction depends. If they are the same, then execution of the load i ...


5
Stephen Van Doren, Rahul Razdan: Distributed data dependency stall mechanism. Compaq Computer Corporation, Hamilton Brook Smith & Reynolds P C, June 19, 2001: US06249846 (37 worldwide citation)

A method and apparatus for preventing system wide data dependent stalls is provided. Requests that reach the top of a probe queue and which target data that is not contained in an attached cache memory, are stalled until the data is filled into the appropriate location in cache memory. Only the asso ...


6
Rahul Razdan, David Arthur James Webb Jr, James Keller, Derrick R Meyer, Daniel Lawrence Leibholz: Method and apparatus for optimizing the performance of LDxL and STxC interlock instructions in the context of a write invalidate protocol. Compaq Computer Corporation, Hamilton Brook Smith & Reynolds P C, October 31, 2000: US06141734 (31 worldwide citation)

A technique for implementing load-locked and store-conditional instruction primitives by using a local cache for information about exclusive ownership. The valid bit in particular provides information to properly execute load-locked and store-conditional instructions without the need for lock flag o ...


7
Rahul Razdan, Michael D Smith: Determining hardware complexity of software operations. Digital Equipment Corporation, March 7, 2000: US06035123 (31 worldwide citation)

A new class of general purpose computers called Programmable Reduced Instruction Set Computers (PRISC) use RISC techniques a basis for operation. In addition to the conventional RISC instructions, PRISC computers provide hardware programmable resources which can be configured optimally for a given u ...


8
Rahul Razdan, Gabriel Bischoff, Ernst G Ulrich: Simulation of circuits. Digital Equipment Corporation, Denis G Maloney, Arthur W Fisher, August 27, 1996: US05550760 (24 worldwide citation)

Computational requirements are reduced for executing simulation code for a logic circuit design having at least some elements which are synchronously clocked by multiple phase clock signals, the simulation code including data structures associated with circuit modules and nodes interconnecting the c ...


9
Han Hsun Chao, Rahul Razdan, Alexander Saldanha: Method and apparatus for critical and false path verification. Cadence Design Systems, John W Carpenter, Reed Smith, March 30, 2004: US06714902 (21 worldwide citation)

A method and apparatus for critical and false path verification takes all the potential false paths and captures the conditions that would make them true paths (or false paths) as a Boolean expression (net list), for the combinational logic only. The net list does not have to be at the gate level, b ...


10
Rahul Razdan, Gabriel Bischoff: Using pre-analysis and a 2-state optimistic model to reduce computation in transistor circuit simulation. Digital Equipment Corporation, Diane C Drozenski, Ronald C Hudgens, Arthur W Fisher, December 2, 1997: US05694579 (17 worldwide citation)

Computational requirements are reduced for executing simulation code for a logic circuit design having at least some elements which are synchronously clocked by multiple phase clock signals, the logic design being subject to resistive conflicts and to charge sharing, the simulation code including da ...