1
Lawrence Henry Hudepohl, Darren Miller Jones, Radhika Thekkath, Franz Treue: Coprocessor interface transferring multiple instructions simultaneously along with issue path designation and/or issue order designation for the instructions. MIPS Technologies, James W Huffman, June 22, 2004: US06754804 (64 worldwide citation)

A configurable coprocessor interface between a central processing unit (CPU) and a coprocessor is provided. The interface groups signals that together comprises all the necessary information for a coprocessor to issue and execute instructions. Multiple issue groups are formed where each group suppor ...


2
George Michael Uhler, Radhika Thekkath: Trace control block implementation and method. MIPS Technologies, Cooley Godward, May 30, 2006: US07055070 (63 worldwide citation)

A system and method for program counter and data tracing is disclosed. A trace interface is provided for communication of trace information between a processor core and a trace control block. The trace interface enables various combinations of processor cores and trace control blocks to be implement ...


3
Radhika Thekkath: Trace control from hardware and software. MIPS Technologies, Cooley Godward Kronish, February 27, 2007: US07185234 (47 worldwide citation)

A system and method for program counter and data tracing is disclosed. The tracing mechanism of the present invention enables increased visibility into the hardware and software state of the processor core.


4
Radhika Thekkath: Burst-configurable data bus. MIPS Technologies, Richard K Huffman, James W Huffman, May 21, 2002: US06393500 (46 worldwide citation)

An apparatus is presented for improving the efficiency of data transactions over a computer system data bus. Bus efficiency is improved by providing a bus master with information to adjust the length and width of burst transactions over the bus to/from target devices. If a particular target device i ...


5
Radhika Thekkath, G Michael Uhler: Coherent data apparatus for an on-chip split transaction system bus. MIPS Technologies, James W Huffman, January 20, 2004: US06681283 (42 worldwide citation)

A cache coherency system for an on-chip computing bus is provided. The coherency system contains a coherency credit counter within each master device on the on-chip bus for monitoring the resources available on the bus for coherent transactions, a coherency input buffer for storing coherent transact ...


6
David A Courtright, Vidya Rajagopalan, Radhika Thekkath, G Michael Uhler: Scalable on-chip system bus. MIPS Technologies, James W Huffman, December 10, 2002: US06493776 (41 worldwide citation)

An on-chip split transaction system bus having separate address and data portions is provided. The system bus contains separate address and data buses for initiating and tracking out-of-order transactions on either or both of the address or data portions of the bus. The system bus provides communica ...


7
Radhika Thekkath, G Michael Uhler: Locked read/write on separate address/data bus using write barrier. MIPS Technologies, Richard K Huffman, James W Huffman, December 3, 2002: US06490642 (35 worldwide citation)

An apparatus is presented for improving the efficiency of data transfers between devices interconnected over an on-chip system bus a multi-master computer system configuration. Bus efficiency is improved by providing an apparatus for controlling a read-modify-write transaction to an address in a bus ...


8
Franz Treue, Radhika Thekkath, Ernest L Edgar, Richard T Leatherman: Optimized external trace formats. MIPS Technologies, Cooley Godward, May 9, 2006: US07043668 (32 worldwide citation)

A system and method for program counter and data tracing is disclosed. Generated trace messages are included within a trace word format and stored in trace memory, thereby enabling a reduction in the amount of trace storage required.


9
David Baker, Christopher Basoglu, Benjamin Cutler, Gregorio Gervasio, Woobin Lee, Yatin Mundkur, Toru Nojiri, John O&apos Donnell, David Poole, Ashok Raman, Eric Rehm, Radhika Thekkath: Data streamer. Hitachi, Equator Technologies, Sofer & Haroun, August 13, 2002: US06434649 (30 worldwide citation)

In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus ar ...


10
David Baker, Christopher Basoglu, Benjamin Cutler, Gregorio Gervasio, Woobin Lee, Yatin Mundkur, Toru Nojiri, John O Donnell, John Poole legal representative, Ashok Raman, Eric Rehm, Radhika Thekkath: Data streamer. Hitachi, Equator Technologies, Sofer & Haroun, June 16, 2009: US07548996 (29 worldwide citation)

In an information processing system which has plurality of modules including a processor, a main memory and a plurality of I/O devices, a data transfer switch for performing data transfer operations between the processor, main memory and I/O devices comprises a request bus which has a request bus ar ...