1
Deepak Pancholi, Manuel Antonio D Abreu, Radhakrishnan Nair, Stephen Skala: Statistical distribution based variable-bit error correction coding. Sandisk Technologies, Toler Law Group PC, October 14, 2014: US08862967 (2 worldwide citation)

A method may be performed at a data storage device that includes a memory and a controller. The method includes providing user data to a variable-bit error correction coding (ECC) encoder. The ECC encoder generates a first set of parity bits. A first number of parity bits in the first set of parity ...


2
Manuel Antonio D Abreu, Stephen Skala, Dimitris Pantelakis, Radhakrishnan Nair, Deepak Pancholi: Smart bridge for memory core. SANDISK TECHNOLOGIES, Toler Law Group PC, December 22, 2015: US09218852 (1 worldwide citation)

An apparatus includes a first semiconductor device including a memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the memory core. The second semiconductor device includes a second serializer/deserializer communication interface coupl ...


3
Baojing Liu, Radhakrishnan Nair, Paul Lassa: Method for performing full transfer automation in a USB controller. SanDisk Corporation, Brinks Hofer Gilson & Lione, September 21, 2010: US07802034 (1 worldwide citation)

A USB controller and method of implementing a full transfer automation mode is described. The USB controller may have a host interface module configured to generate hardware logic signals for communication to a backend module having buffer memory. The backend module may be configured to generate har ...


4
Mike Yang Chang Guo, Soo Yao Jee, Radhakrishnan Nair Oravielil Kamalashi: Respiratory therapy device having standard and oscillatory PEP with nebulizer. Hill Rom Services, Barnes & Thornburg, November 10, 2015: US09180271

A respiratory therapy device has both a standard positive expiratory pressure (PEP) device and an oscillatory PEP device packaged together. A manually operable member is movable to select which of the standard and oscillatory PEP device is placed in communication with a patient's airway. A nebulizer ...


5
Manuel Antonio D Abreu, Stephen Skala, Dimitris Pantelakis, Radhakrishnan Nair, Deepak Pancholi: Smart bridge for memory core. SANDISK TECHNOLOGIES, Toler Law Group PC, November 3, 2015: US09177610

An apparatus includes a semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a differen ...


6
Manuel Antonio D Abreu, Stephen Skala, Dimitris Pantelakis, Radhakrishnan Nair, Deepak Pancholi: Smart bridge for memory core. SANDISK TECHNOLOGIES, Toler Law Group PC, November 3, 2015: US09177611

An apparatus includes a first semiconductor device including a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory further includes circuitry associated with operation of the multiple memory cells. The appa ...


7
Manuel Antonio D Abreu, Stephen Skala, Dimitris Pantelakis, Radhakrishnan Nair, Deepak Pancholi: Smart bridge for memory core. SANDISK TECHNOLOGIES, Toler Law Group PC, November 3, 2015: US09177612

An apparatus includes a semiconductor device that includes a multi-ported three-dimensional (3D) memory. The multi-ported 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The multi-ported 3D memory includes circuitry associated with operation of the mu ...


8
Manuel Antonio D Abreu, Stephen Skala, Dimitris Pantelakis, Radhakrishnan Nair, Deepak Pancholi: Smart bridge for memory core. SANDISK TECHNOLOGIES, Toler Law Group PC, September 22, 2015: US09142261

An apparatus includes a semiconductor device that includes a three-dimensional (3D) memory. The 3D memory includes multiple memory cells arranged in multiple physical levels above a substrate. The 3D memory includes circuitry associated with operation of the multiple memory cells and includes a seri ...


9
Manuel Antonio D Abreu, Stephen Skala, Dimitris Pantelakis, Radhakrishnan Nair, Deepak Pancholi: Smart bridge for memory core. SANDISK TECHNOLOGIES, Toler Law Group PC, November 3, 2015: US09177609

An apparatus includes a first memory die including a first memory core, a second memory die including a second memory core, and a periphery die coupled to the first memory die and to the second memory die. The periphery die includes periphery circuitry corresponding to the first memory core and peri ...


10
Manuel Antonio D Abreu, Stephen Skala, Dimitris Pantelakis, Radhakrishnan Nair, Deepak Pancholi: Smart bridge for memory core. SANDISK TECHNOLOGIES, Toler Law Group PC, August 2, 2016: US09406346

An apparatus includes a first semiconductor device including a NAND flash memory core. The apparatus also includes a second semiconductor device including periphery circuitry associated with the NAND flash memory core.