1
Qiong Cai, José González, Pedro Chaparro Monferrer, Grigorios Magklis, Antonio González: Thread migration to improve power efficiency in a parallel processing environment. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 19, 2011: US07930574 (9 worldwide citation)

A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing co ...


2
Serkan Ozdemir, Qiong Cai: Endurance aware error-correcting code (ECC) protection for non-volatile memories. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 24, 2015: US08990670 (5 worldwide citation)

Embodiments of the invention relate to endurance-aware ECC protection for memories (e.g., phase change memories). According to one embodiment, a method includes calculating first metadata for data bits and second metadata for ECC bits which protect the data bits and the first metadata. Embodiments c ...


3
Antonio Gonzalez, Qiong Cai, Jose Gonzalez, Pedro Chaparro, Grigorios Magklis, Ryan Rakvic: Meeting point thread characterization. Intel Corporation, Trop Pruner & Hu P C, February 16, 2010: US07665000 (4 worldwide citation)

An apparatus associated with identifying a critical thread based on information gathered during meeting point processing is provided. One embodiment of the apparatus may include logic to selectively update meeting point counts for threads upon determining that they have arrived at a meeting point. T ...


4
Qiong Cai, José González, Pedro Chaparro Monferrer, Grigorios Magklis, Antonio González: Thread migration to improve power efficiency in a parallel processing environment. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 24, 2012: US08166323 (3 worldwide citation)

A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing co ...


5
Grigorios Magklis, Jose Gonzalez, Pedro Chaparro, Qiong Cai, Antonio Gonzalez: Compressing address communications between processors. Intel Corporation, Trop Pruner & Hu P C, April 13, 2010: US07698512 (2 worldwide citation)

In one embodiment, the present invention includes a method for determining if data of a memory request by a first agent is in a memory region represented by a region indicator of a region table of the first agent, and transmitting a compressed address for the memory request to other agents of a syst ...


6
Qiong Cai, Nevin Hyuseinova, Serkan Ozdemir, Ferad Zyulkyarov, Marios Nicolaides, Blas Cuesta: Apparatus, system and method for adaptive cache replacement in a non-volatile main memory system. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 7, 2015: US09003126 (1 worldwide citation)

Techniques and mechanisms for adaptively changing between replacement policies for selecting lines of a cache for eviction. In an embodiment, evaluation logic determines a value of a performance metric which is for writes to a non-volatile memory. Based on the determined value of the performance met ...


7
Nevin Hyuseinova, Qiong Cai, Serkan Ozdemir, Ayose J Falcon: Utility and lifetime based cache replacement policy. Intel Corporation, Nicholson De Vos Webster & Elliott, July 7, 2015: US09075746 (1 worldwide citation)

Embodiments of the invention describe an apparatus, system and method for utilizing a utility and lifetime based cached replacement policy as described herein. For processors having one or more processor cores and a cache memory accessible via the processor core(s), embodiments of the invention desc ...


8
Ferad Zyulkyarov, Nevin Hyuseinova, Qiong Cai, Blas Cuesta, Serkan Ozdemir, Marios Nicolaides: Method for pinning data in large cache in multi-level memory system. Intel Corporation, Trop Pruner & Hu P C, May 9, 2017: US09645942

A method to request memory from a far memory cache and implement, at an operating system (OS) level, a fully associative cache on the requested memory. The method includes pinning the working set of a program into the requested memory (pin buffer) so that it is not evicted due to cache conflicts and ...


9
Nevin Hyuseinova, Qiong Cai: Page miss handler including wear leveling logic. Intel Corporation, Nicholson De Vos Webster & Elliott, February 16, 2016: US09262336

Embodiments of the invention describe an apparatus, system and method for utilizing a page miss handler having wear leveling logic/modules for memory devices. Embodiments of the invention may track an amount of writes directed towards cells of a memory device, and determine whether a linear address ...


10
Dyer Rolan, Nevin Hyuseinova, Blas A Cuesta, Qiong Cai: Method, apparatus and system to cache sets of tags of an off-die cache memory. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 31, 2017: US09558120

Techniques and mechanism to provide a cache of cache tags in determining an access to cached data. In an embodiment, a tag storage stores a first set including tags associated with respective data locations of a cache memory. A cache of cache tags store a subset of tags stored by the tag storage. In ...