1
Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Logic cell array and bus system. Pact XPP Technologies, Kenyon & Kenyon, September 29, 2009: US07595659 (46 worldwide citation)

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separa ...


2
Ashutosh Joshi, Aparna Gupta, Binay Mohanty, Jalvin Upadhyay, Rajiv Arora, Martin Betz, Michael Prospero, David Cooke, Prashant Rao: Event naming. Firstrain, Adeli & Tollen, June 11, 2013: US08463790 (23 worldwide citation)

Some embodiments provide a machine-implemented method. The method identifies an event for a particular category based on a number of documents classified as relevant to the particular category in a particular period of time. Based on content of the documents classified as relevant to the particular ...


3
Ashutosh Joshi, Aparna Gupta, Binay Mohanty, Jalvin Upadhyay, Rajiv Arora, Martin Betz, Michael Prospero, David Cooke, Prashant Rao: Event detection. Firstrain, Adeli & Tollen, June 11, 2013: US08463789 (6 worldwide citation)

Some embodiments provide a method for identifying an event for a particular category. The method classifies several documents as relevant to several different categories. The method identifies a number of documents relevant to the particular category for a current time period and a background time p ...


4
Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Logical cell array and bus system. PACT XPP TECHNOLOGIES, Edward P Heller III, June 2, 2015: US09047440 (5 worldwide citation)

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separa ...


5
Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Logic cell array and bus system. Bechen PLLC, June 25, 2013: US08471593 (2 worldwide citation)

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separa ...


6
Sindhu K Mohandas, Prashant Rao: System and method for traffic distribution in a multi-chassis link aggregation. Alcatel Lucent, Garlick & Marksion, Jessica W Smith, July 16, 2013: US08488608 (2 worldwide citation)

A pair of aggregation switches is connected to an edge node by a multi-chassis link aggregation group, wherein the aggregation switches are connected by a virtual fabric link (VFL) for exchange of information between the Aggregation Switches. The VFL includes a plurality of subsets of VFL physical l ...


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Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Logic cell array and bus system. Kenyon & Kenyon, November 15, 2011: US08058899 (1 worldwide citation)

A logic cell array having a number of logic cells and a segmented bus system for logic cell communication, the bus system including different segment lines having shorter and longer segments for connecting two points in order to be able to minimize the number of bus elements traversed between separa ...


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Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Data processor chip with flexible bus system. PACT XPP TECHNOLOGIES, Edward P Heller III, February 9, 2016: US09256575

A data processor chip having a two-dimensional array of arithmetic logic units and memory where the arithmetic logic units are in communication with memory units in one dimension and with other arithmetic units in a second.


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Martin Vorbach, Frank May, Dirk Reichardt, Frank Lier, Gerd Ehlers, Armin Nückel, Volker Baumgarte, Prashant Rao, Jens Oertel: Array processor having a segmented bus system. PACT XPP TECHNOLOGIES, Edward P Heller III, April 18, 2017: US09626325

An array processor on integrated circuit chip. The array processor has a plurality of memories and a segmented bus system, wherein each segment is selectively connectable to other segments and wherein each segment has a plurality of selectable data paths. A segment is connected to each array process ...


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Surya Prashant Rao, Darpan Majumder: Method and device for wireless communications on multiple frequency bands. Fay Kaplun & Marcin, December 6, 2007: US20070281634-A1

Described is a method and device for wireless communications on multiple frequency bands. The device comprises a communications arrangement and a processor. The communications arrangement receives radio frequency (RF) maps from a plurality of wireless communication devices. The RF maps are indicativ ...