1
Valery M Dubin, Yosi Schacham Diamand, Bin Zhao, Prahalad K Vasudev, Chiu H Ting: Use of cobalt tungsten phosphide as a barrier material for copper metallization. Cornell Research Foundation, Sematech, Intel Corporation, William W Kidd, December 9, 1997: US05695810 (439 worldwide citation)

A technique for electrolessly depositing a CoWP barrier material on to copper and electrolessly depositing copper onto a CoWP barrier material to prevent copper diffusion when forming layers and/or structures on a semiconductor wafer.


2
Bin Zhao, Prahalad K Vasudev, Valery M Dubin, Yosef Shacham Diamand, Chiu H Ting: Selective electroless copper deposited interconnect plugs for ULSI applications. Sematech, Kidd & Booth, October 7, 1997: US05674787 (418 worldwide citation)

A method or utilizing electroless copper deposition to selectively form encapsulated copper plugs to connect conductive regions on a semiconductor. A via opening in an inter-level dielectric (ILD) provides a path for connecting two conductive regions separated by the ILD. Once the underlying metal l ...


3
Yosef Schacham Diamand, Valery M Dubin, Chiu H Ting, Bin Zhao, Prahalad K Vasudev, Melvin Desilva: Protected encapsulation of catalytic layer for electroless copper interconnect. Cornell Research Foundation, Intel Corporation, Sematech, October 20, 1998: US05824599 (299 worldwide citation)

A method for utilizing electroless copper deposition to form interconnects on a semiconductor. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is deposited. Then, a catalytic copper seed layer is conformally blanket deposited in vacuum ...


4
Valery M Dubin, Yosef Shacham Diamand, Chiu H Ting, Bin Zhao, Prahalad K Vasudev: Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications. Cornell Research Foundation, Intel Corporation, Sematech, April 6, 1999: US05891513 (262 worldwide citation)

A method of utilizing electroless copper deposition to form interconnects on a semiconductor wafer. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is blanket deposited. Then, a contact displacement technique is used to form a thin acti ...


5
Yosi Shacham Diamand, Valery M Dubin, Chiu H Ting, Bin Zhao, Prahalad K Vasudev: Electroless deposition equipment or apparatus and method of performing electroless deposition. Cornell Research Foundation, Sematech, Intel Corporation, November 3, 1998: US05830805 (175 worldwide citation)

An electroless deposition apparatus and a method of electroless deposition that uses a single process chamber for performing multiple processes by moving through the process chamber a variety of fluids one at a time in a sequential order.


6
Prahalad K Vasudev: Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing. Hughes Aircraft Company, Victor G Laslo, A W Karambelas, October 14, 1986: US04617066 (144 worldwide citation)

A method for producing hyperabrupt P.+-. or N.+-. regions in a near-surface layer of a substantially defect free crystal, using solid phase epitaxy and transient annealing. The process for producing a hyperabrupt retrograde distribution of the dopant species begins with amorphizing the near-surface ...


7
Prahalad K Vasudev: Globally planarized binary optical mask using buried absorbers. Sematech, William W Kidd, December 12, 1995: US05474865 (143 worldwide citation)

A globally planarized binary optical mask has absorbers embedded (buried) in the mask substrate, instead of on the surface of the mask. Light scattering at rough vertical edges of absorbers of prior art masks are reduced or eliminated. Also, due to the buried nature of the absorbers, a triple singul ...


8
Bin Zhao, Prahalad K Vasudev, Ronald S Horwath, Thomas E Seidel, Peter M Zeitzoff: Dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer. March 14, 2000: US06037664 (141 worldwide citation)

A technique for fabricating a dual damascene interconnect structure using a low dielectric constant material as a dielectric layer or layers. A low dielectric constant (low-.epsilon.) dielectric material is used to form an inter-level dielectric (ILD) layer between metallization layers and in which ...


9
Bin Zhao, Prahalad K Vasudev, Ronald S Horwath, Thomas E Seidel, Peter M Zeitzoff: Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer. Sematech, Lucent Technologies, August 8, 2000: US06100184 (102 worldwide citation)

A technique for fabricating a dual damascene interconnect structure using a low dielectric constant material as a dielectric layer or layers. A low dielectric constant (low-.di-elect cons.) dielectric material is used to form an inter-level dielectric (ILD) layer between metallization layers and in ...


10
Prahalad K Vasudev: Opposed dual-gate hybrid structure for three-dimensional integrated circuits. Hughes Aircraft Company, Terje Gudmestad, Paul M Coble, A W Karambelas, May 31, 1988: US04748485 (85 worldwide citation)

A three-dimensional integrated circuit structure utilizing a hybridization of silicon-on-insulator and silicon-on-sapphire technologies is disclosed, wherein a buried doped epitaxial silicon layer, insulated from a gated semiconductor device by a buried insulating layer, biases the gate region of th ...