1
Syed M Alam, Ibrahim M Elfadel, Kathryn W Guarini, Meikei Ieong, Prabhakar N Kudva, David S Kung, Mark A Lavin, Arifur Rahman: Three dimensional integrated circuit. International Business Machines Corporation, Law Office of Charles W Peterson Jr, Louis J Percello Esq, Rafael Perez Piniero Esq, December 25, 2007: US07312487 (117 worldwide citation)

A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to ...


2
Syed M Alam, Ibrahim M Elfadel, Kathryn W Guarini, Meikei Ieong, Prabhakar N Kudva, David S Kung, Mark A Lavin, Arifur Rahman: Three dimensional integrated circuit and method of design. International Business Machines Corporation, Law Office of Charles W Peterson Jr, Brian P Verminski Esq, May 25, 2010: US07723207 (85 worldwide citation)

A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to ...


3
Pradip Bose, Alper Buyuktosunoglu, Chen Yong Cher, Prabhakar N Kudva: Method and system for controlling power in a chip through a power-performance monitor and control unit. International Business Machines Corporation, Keusey Tutunjian & Bitetto P C, Mark Wardas, September 2, 2008: US07421601 (28 worldwide citation)

A system and method for controlling power and performance in a microprocessor system includes a monitoring and control system integrated into a microprocessor system. The monitoring and control system includes a hierarchical architecture having a plurality of layers. Each layer in the hierarchical a ...


4
Hans M Jacobson, Pradip Bose, Alper Buyuktosunoglu, Peter William Cook, Philip George Emma, Prabhakar N Kudva, Stanley Everett Schuster: Method and structure for short range leakage control in pipelined circuits. International Business Machines Corporation, Keusey Tutunjian & Bitetto P C, Satheesh K Karra Esq, September 20, 2005: US06946869 (18 worldwide citation)

Leakage current control devices include a circuit having one or more functions in a data path where the functions are executed in a sequence. Each of the functions has power reduction logic to energize each respective function. A leakage control circuit interacts with the power reduction logic, so t ...


5
Hans M Jacobson, Prabhakar N Kudva, Pradip Bose, Peter W Cook, Stanley E Schuster: Interlocked synchronous pipeline clock gating. International Business Machines Corporation, Law Office of Charles W Peterson Jr, Louis J Percello Esq, Satheesh K Karra Esq, June 20, 2006: US07065665 (16 worldwide citation)

An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a d ...


6
Pradip Bose, Daniel M Citron, Peter W Cook, Philip G Emma, Hans M Jacobson, Prabhakar N Kudva, Stanley E Schuster, Jude A Rivers, Victor V Zyuban: Processor with demand-driven clock throttling power reduction. International Business Machines Corporation, Law Office of Charles W Peterson Jr, Louis J Percello Esq, Satheesh K Karra Esq, July 11, 2006: US07076681 (15 worldwide citation)

A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clock ...


7
Pradip Bose, Alper Buyuktosunoglu, Chen Yong Cher, Zhigang Hu, Hans Jacobson, Prabhakar N Kudva, Vijayalakshmi Srinivasan, Victor Zyuban: Method and system of peak power enforcement via autonomous token-based control and management. International Business Machines Corporation, F Chau & Associates, William J Stock Esq, April 19, 2011: US07930578 (6 worldwide citation)

A method of power management of a system of connected components includes initializing a token allocation map across the connected components, wherein each component is assigned a power budget as determined by a number of allocated tokens in the token allocation map, monitoring utilization sensor in ...


8
Hans M Jacobson, Prabhakar N Kudva, Leon J Sigal: System and method for topology selection to minimize leakage power during synthesis. International Business Machines Corporation, F Chau & Associates, August 29, 2006: US07100144 (6 worldwide citation)

A system for topology selection to minimize leakage power during synthesis, wherein the system is configured to receive a circuit model that has one or more circuit gates. The system is further configured to receive a library having one or more logic gates, wherein each logic gate has a topology and ...


9
Hans M Jacobson, Prabhakar N Kudva, Peter W Cook, Stanley Everett Schuster: Circuit structures and methods for high-speed low-power select arbitration. International Business Machines Corporation, F Chau & Associates, January 28, 2003: US06512397 (6 worldwide citation)

A method is provided for selecting a participant to issue. The method includes signaling a domino OR gate arbitration device upon a ready request of a participant having a priority, determining within the domino OR gate arbitration device the relative priority of the participant, signaling the domin ...


10
Wilm E Donath, Prabhakar N Kudva: Method for improving the assignment of circuit locations during fabrication. International Business Machines Corporation, F Chau & Associates, November 6, 2001: US06314547 (5 worldwide citation)

The method for improving circuit location assignment is capable of operating in the boolean, electrical and spatial (location) domains. Optimization of location assignment parameters can be performed simultaneously by determining a subset of nets or paths and generating sets of motions to improve th ...



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