1
Lars W Liebmann, Mark A Lavin, Pia N Sanda: Geometric autogeneration of "hard" phase-shift designs for VLSI. International Business Machines Corporation, Charles W Peterson, Whitham Curtis Whitham & McGinn, July 16, 1996: US05537648 (54 worldwide citation)

A method implemented in a computer aided design (CAD) system automatically generates phase shifted mask designs for very large scale integrated (VLSI) chips from existing circuit design data. The system uses a series of basic geometric operations to design areas requiring phase assignment, resolve c ...


2
Lars W Liebmann, Mark A Lavin, Pia N Sanda: Geometric autogeneration of"hard"phase-shift designs for VLSI. International Business Machines Corporation, Charles W Peterson Jr, Whitham Curtis Whitham & McGinn, June 3, 1997: US05636131 (40 worldwide citation)

An apparatus implemented in a computer aided design (CAD) system automatically generates phase shifted mask designs for very large scale integrated (VLSI) chips from existing circuit design data. The system uses a series of basic geometric operations to design areas requiring phase assignment, resol ...


3
Daniel R Knebel, Mark A Lavin, Jamie Moreno, Stanislav Polonsky, Pia N Sanda, Steven H Voldman: System and method for VLSI visualization. International Business Machines Corporation, Scully Scott Murphy & Presser, Richard M Ludwin, May 17, 2005: US06895372 (28 worldwide citation)

A method and system for visualizing circuit operation. In the method device activity is obtained based on one or more of measured or simulated activity. The device activity is expressed in a representation, and the expressed activity is represented in a visual form. One suitable form of activity is ...


4
Harold W Chase, Daniel R Knebel, Dennis G Menzer, Stanislav Polonsky, Pia N Sanda: Method for VLSI system debug and timing analysis. International Business Machines Corporation, Scully Scott Murphy & Presser, Marian Underweiser Esq, September 26, 2006: US07114136 (4 worldwide citation)

A method for characterizing circuit activity in an IC. Generally, the method comprises the steps of activating an IC, resolving the switching activity in space and time, and generating a representation of the switching behavior which differentiates the time that circuits or transistors switch. One e ...


5
Robert Brett Tremaine, Mark Anthony Check, Pia N Sanda, Prabhakar Nandavar Kudva: Verification of soft error resilience. International Business Machines Corporation, Cantor Colburn, John Campbell, October 8, 2013: US08555234 (1 worldwide citation)

An efficient method for selecting a minimal and statistically relevant set of SER sensitive logic devices critical to the SER robustness for a design, through identification by device type, identification nomenclature, connectivity and context. The minimal set of devices comprise the set of fault in ...


6
Pradip Bose, Prabhakar N Kudva, Jude A Rivers, Pia N Sanda, John David Wellman: Modeling system-level effects of soft errors. International Business Machines Corporation, Stephen J Walder Jr, William Stock, January 3, 2012: US08091050 (1 worldwide citation)

Mechanisms for modeling system level effects of soft errors are provided. Mechanisms are provided for integrating device-level and component-level soft error rate (SER) analysis mechanisms with micro-architecture level performance analysis tools during a concept phase of the IC design to thereby gen ...


7
Harold W Chase, Daniel R Knebel, Dennis G Menzer, Stanislay Polonsky, Pia N Sanda: Method for VLSI system debug and timing analysis. International Business Machines Corporation, Scully Scott Murphy & Presser PC, November 24, 2005: US20050262454-A1

A method for characterizing circuit activity in an IC. Generally, the method comprises the steps of activating an IC, resolving the switching activity in space and time, and generating a representation of the switching behavior which differentiates the time that circuits or transistors switch. One e ...


8
Robert Brett Tremaine, Mark Anthony Check, Pia N Sanda, Prabhakar Nandavar Kudva: Verification of Soft Error Resilience. International Business Machines Corporation, March 3, 2011: US20110055777-A1

An efficient method for selecting a minimal and statistically relevant set of SER sensitive logic devices critical to the SER robustness for a design, through identification by device type, identification nomenclature, connectivity and context. The minimal set of devices comprise the set of fault in ...


9
Pradip Bose, Prabhakar N Kudva, Jude A Rivers, Pia N Sanda, John David Wellman: Modeling System-Level Effects of Soft Errors. International Business Machines Corporation, IBM, c o Walder Intellectual Property Law PC, April 1, 2010: US20100083203-A1

Mechanisms for modeling system level effects of soft errors are provided. Mechanisms are provided for integrating device-level and component-level soft error rate (SER) analysis mechanisms with micro-architecture level performance analysis tools during a concept phase of the IC design to thereby gen ...



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